Dual Voltage Memory Circuit Level Shifting
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Solution Overview
Problem
As integrated memory circuits are scaled down, reducing power supply voltage leads to increased memory write and read errors due to sensitivity of memory cells and sense amplifiers, while implementing a dual power supply configuration with level shifters consumes additional energy and increases chip area and signal propagation delay.
Innovation Solution
A dual voltage memory circuit design that operates memory cells at a higher voltage (0-1.3V) and support circuits at a lower voltage (0-0.7V), using level shifters to transition signals between these voltage levels, and a timing tracking circuit to synchronize clock signals, reducing the need for multiple level shifters and minimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If voltage is reduced to decrease power consumption, then power consumption decreases, but memory write and read errors increase
Solution Approach 1:
The patent applies different voltage levels to different parts of the memory circuit: memory cells operate at higher voltage (1.3V) to maintain data integrity, while support circuits operate at lower voltage (0.7V) to reduce power consumption. This local differentiation resolves the contradiction by allowing each component to operate at its optimal voltage level.
Solution Approach 2:
The memory circuit is segmented into two distinct power domains: a first power domain for memory cells operating at higher voltage and a second power domain for support circuits operating at lower voltage. This segmentation enables independent voltage control, allowing power reduction in support circuits without affecting memory cell reliability.
2Adaptability or versatility
If level shifters are added to interface components operating at different voltages, then voltage compatibility is achieved, but chip area and power consumption increase
Solution Approach 1:
The patent merges the level shifting function into the decoder circuitry itself rather than using separate level shifter components. The decoder simultaneously performs address decoding and voltage level translation, eliminating dedicated level shifter blocks and reducing chip area while maintaining voltage compatibility between domains.
Solution Approach 2:
The decoder circuit is designed to perform multiple functions: address decoding, word line selection, and voltage level translation. This multi-functional approach eliminates the need for separate level shifter components, reducing both chip area and overall power consumption while achieving voltage compatibility.
3Adaptability or versatility
If level shifters are used to convert voltage levels, then signal translation is achieved, but signal propagation delay increases
Solution Approach 1:
The level shifting operation is merged with the decoder's natural signal path, allowing voltage translation to occur concurrently with address decoding rather than as a separate sequential step. This integration minimizes additional propagation delay while achieving the required voltage level translation.
Solution Approach 2:
The decoder circuit is pre-designed with integrated level shifting capability, so the voltage translation function is already in place and optimized within the signal path. This preliminary integration ensures minimal additional delay compared to adding discrete level shifters after the fact.
Data Source
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AI summary
A semiconductor memory device includes address signal level shifters configured to transform a low level address signal into a higher level address signal. A decoder (102) is configured to receive the higher level address signal and, in response, provide word line signals. Write drivers (305) receive low level data input signals and configure bitlines (109) in response to the received input. Memory cells (111) are responsive to the word line signals and to the configured bit lines for storing data therein.