SRAM Ripple Bit Lines for Leakage and Density
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Solution Overview
Problem
Advanced semiconductor processes for static random access memories (SRAM) face challenges with current leakage and process variation tolerance, leading to reduced stability and increased power consumption due to bit line connections and the need for additional metal layers.
Innovation Solution
The implementation of a static random access memory with a pre-charger, local bit lines, and ripple buffers that connect cell column arrays in series, allowing for efficient data transfer between local bit lines without the need for a global bit line, thereby reducing current leakage and increasing density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If bit lines connect more SRAM cells to increase density, then storage capacity increases, but current leakage increases and sense margin reduces
Solution Approach 1:
The patent divides the bit line into multiple segments: local bit lines (LBLs) that connect to cell columns and ripple buffers that connect LBLs in series. This segmentation allows the bit line to serve multiple cell columns without creating a single long bit line with excessive leakage, thus maintaining high density while controlling current leakage through distributed architecture.
2Speed
If global bit lines are used to connect all cell columns, then access speed improves, but read disturbance increases and sense margin decreases
Solution Approach 1:
The patent replaces the single global bit line with multiple local bit lines connected through ripple buffers. Each local bit line serves a specific cell column, enabling independent operation and reducing read disturbance to other columns while maintaining fast access through the ripple buffer propagation mechanism.
Solution Approach 2:
The ripple buffer acts as an intermediary component between local bit lines and global bit lines. It mediates the signal transmission by receiving signals from local bit lines and propagating them through the array, enabling coordinated access across multiple columns without direct global bit line connections that cause read disturbance.
3Loss of energy
If shorter local bit lines are used to reduce leakage, then sense margin improves, but chip area increases due to additional metal layers
Solution Approach 1:
The patent merges the ripple buffer function with the bit line structure, integrating the signal propagation mechanism directly into the bit line architecture. This consolidation eliminates the need for separate global bit line metal layers while maintaining the benefits of short local bit lines, thus reducing chip area without sacrificing leakage control or sense margin.
4Adaptability or versatility
If additional metal layers are added for global bit lines, then connectivity improves, but manufacturing complexity increases
Solution Approach 1:
The patent combines multiple bit line functions into a single metal layer by integrating ripple buffers directly into the bit line structure. This merging approach maintains comprehensive connectivity across cell columns while avoiding the need for additional metal layers, thus simplifying the manufacturing process without sacrificing adaptability or versatility.
Data Source
AI summary
A static random access memory includes a pre-charger, a first cell column array/peripheral circuit, and a first ripple buffer. The pre-charger is connected to a first local bit line in order to pre-charge the first local bit line. The first cell column array/peripheral circuit is connected to the first local bit line and has a plurality of cells for temporarily storing data. The cells are connected to the first local bit line. The first ripple buffer is connected to the first local bit line and a second local bit line in order to send the data from the first local bit line to the second local bit line.