Adjustable Write Pulse Generation Circuit for FPGA Memory

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Conventional LUTRAM data write schemes in FPGAs lack an interrelationship between write time and write pulse width, leading to suboptimal dynamic write margin across PVT conditions, which hampers performance.

Innovation Solution

The introduction of a write pulse generation circuit that dynamically adjusts write pulse width based on write time, optimizing write performance by ensuring low write pulse transitions post-write operation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional fixed write pulse width is used, then circuit simplicity is maintained, but write performance is suboptimal across PVT conditions

Engineering Contradiction:

Improvewrite performanceVSAvoidwrite pulse generation circuit

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements dynamic adjustment of write pulse width based on actual write operation completion status. The write pulse generation circuit transitions from fixed width to variable width by monitoring write operation status and adjusting pulse duration accordingly, optimizing write performance across different PVT conditions while managing circuit complexity through targeted dynamic behavior.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent changes the write pulse width parameter dynamically based on write operation requirements. By adjusting the pulse width parameter in response to write completion status and PVT conditions, the system optimizes write performance without requiring complete redesign of the pulse generation circuit, balancing reliability improvement with acceptable complexity increase.

Inventive Principle:

Principle #35Parameter changes

2Reliability

If write pulse width is increased to ensure complete write operations, then write reliability improves, but power consumption increases

Engineering Contradiction:

Improvewrite operation completionVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent dynamically adjusts write pulse width based on actual write operation needs rather than using a consistently wide pulse. By monitoring write completion status and adjusting pulse duration in real-time, the system ensures reliable write operations when needed while minimizing pulse width (and thus power consumption) during normal operations, resolving the contradiction between reliability and power usage.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent applies write pulse width adjustment selectively rather than continuously. Instead of always using excessive pulse width to guarantee write completion, the system applies increased pulse width only when write operations require it, based on status monitoring and PVT conditions. This partial application of excessive action ensures reliability while avoiding unnecessary power consumption during operations that don't require extended pulse width.

Inventive Principle:

Principle #16Partial or excessive action

Data Source

PatentUS20250022495A1Circuits And Methods For Generating Adjustable Signal Pulses That Control Writes To Memory Cells

Publication Date: 2025.01.16 ALTERA CORP

AI summary

An integrated circuit includes a memory bit cell having a transistor coupled to a data line and a write pulse generation circuit coupled to the memory bit cell. The write pulse generation circuit generates a pulse in a word line signal that controls the transistor. The write pulse generation circuit adjusts a width of the pulse in the word line signal based on a write time of a write operation to the memory bit cell performed through the data line and the transistor.