Synchronization Circuit for DDR Memory Write Operations
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Solution Overview
Problem
In DDR graphics memories, gapless write commands cause overlapping of signal edges, leading to misinterpretation of data packets and improper latching, especially at high operating frequencies, due to synchronization issues between the WDQS signal and the internal clock signal.
Innovation Solution
A synchronization circuit using two FIFOs, one for data and one for addresses, decouples the data storage from the WDQS signal timing, allowing for independent operation and accurate identification of gapless and gapped write commands, ensuring proper data latching regardless of signal synchronization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If gapless write commands are used to increase write speed, then productivity is improved, but reliability deteriorates due to overlapping signal edges causing misinterpretation of data packets
Solution Approach 1:
A synchronization circuit is introduced as an intermediary component between the WDQS signal and the internal clock domain. This circuit includes flip-flops that capture the preamble and postamble signals on the internal clock edge, acting as a mediator that translates the WDQS timing information into the internal clock domain, thereby preventing direct conflict between overlapping signals while maintaining high write speed
Solution Approach 2:
The synchronization circuit performs preliminary action by capturing and storing the preamble signal state before the actual data latching occurs. By pre-capturing the WDQS signal state at the appropriate clock edge, the system prepares the necessary timing information in advance, allowing subsequent data packets to be correctly identified and latched even in gapless write command scenarios
2Ease of operation
If the counter is directly synchronized with the WDQS signal, then ease of operation is improved, but measurement precision deteriorates due to phase differences between WDQS and internal clock signals
Solution Approach 1:
Instead of attempting to fully synchronize the counter with the WDQS signal phase, the solution uses partial synchronization by capturing only the critical preamble and postamble timing information at specific clock edges. This partial action approach captures sufficient timing information to correctly identify data packets without requiring complete phase alignment, thereby maintaining both operational simplicity and timing accuracy
Solution Approach 2:
The synchronization circuit creates a copy of the WDQS signal timing information by capturing the preamble state in flip-flops. This copied timing information is then used in the internal clock domain to control the counter and data latching, eliminating the need for direct WDQS synchronization while preserving the essential timing relationships
Data Source
AI summary
A synchronization circuit for handling and synchronizing a write operation on a semiconductor memory, in which a write operation contains a plurality of write commands, comprises a controllable first FIFO and a controllable second FIFO. The first FIFIO is clocked by a WDQS signal and stores write data on the basis of one or more successive write commands. The second FIFO is clocked by an internal clock signal and stores, for a write operation, only addresses associated with valid write data of the write data stored in the first FIFO.