Semiconductor Memory Module Failover Controller

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Solution Overview

Problem

Current semiconductor memory modules face limitations in storage capacity and reliability due to the failure of data buffers, which can lead to data loss and uncorrectable read errors, especially when volatile and nonvolatile memory devices are used in conjunction with limited data buffers.

Innovation Solution

A semiconductor memory system with a controller that performs a failover operation by identifying and bypassing failed data buffers, using a failover data buffer to ensure data integrity and availability, thereby preventing data loss and read errors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If data buffers are used to manage data between volatile and nonvolatile memory devices, then data transfer efficiency is improved, but system reliability deteriorates when data buffers fail

Engineering Contradiction:
Improvedata transfer efficiencyVSAvoidsystem reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent implements a failover mechanism that prepares alternative data paths in advance. When a data buffer fails, the system can switch to using other available data buffers or memory devices to continue operations, preventing total system failure and maintaining reliability while preserving data transfer efficiency through the failover path

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

2Speed

If volatile memory devices are used for high-speed access, then access speed is improved, but data loss risk increases when power is lost

Engineering Contradiction:
Improveaccess speedVSAvoiddata persistence
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent introduces nonvolatile memory devices as an intermediary layer between the volatile memory and the external device. Data can be quickly accessed from volatile memory when needed, and the system ensures data integrity by having the capability to retrieve data from nonvolatile memory if volatile memory data is lost, thus maintaining both speed and reliability

Inventive Principle:
Principle #24Intermediary (Mediator)

3Quantity of substance

If nonvolatile memory devices are used for large storage capacity, then storage capacity is improved, but access speed deteriorates

Engineering Contradiction:
Improvestorage capacityVSAvoidaccess speed
Core Design Contradiction:
Quantity of substanceVSSpeed

Solution Approach 1:

The patent segments the memory system into volatile and nonvolatile memory devices, each serving different purposes. Volatile memory handles high-speed access for frequently accessed data, while nonvolatile memory provides large storage capacity for data that doesn't require immediate access. The controller intelligently manages data placement and retrieval between these segments, achieving both high speed and large capacity

Inventive Principle:
Principle #1Segmentation

4Reliability

If data buffer failure occurs, then data integrity is compromised, but system complexity increases with failover mechanisms

Engineering Contradiction:
Improvedata integrityVSAvoidsystem complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements a self-service failover mechanism where the system automatically detects data buffer failures and switches to alternative data paths without requiring complex external intervention. The failover logic is integrated into the controller, which autonomously manages the switching process, thereby maintaining data integrity while minimizing the increase in system complexity

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS10698781B2Semiconductor memory module, semiconductor memory system, and method of accessing semiconductor memory module
Publication Date: 2020.06.30 SAMSUNG ELECTRONICS CO LTD
  • US10698781B2 patent drawing
  • US10698781B2 patent drawing
  • US10698781B2 patent drawing

AI summary

A semiconductor memory module includes a volatile memory device, a nonvolatile memory device, data buffers, and a controller. The controller outputs first data read from the volatile memory device or the nonvolatile memory device to an external device through the data buffers, and writes second data received from the external device through the data buffers in the volatile memory device or the nonvolatile memory device. The controller performs a failover operation depending on a failover request that includes fail information indicating a position of a failed data buffer among the data buffers. In the failover operation, the controller conveys third data associated with the failed data buffer to the external device through a failover data buffer among the data buffers.