3D Memory Array With Vertical Bit Lines Reducing Leakage Current
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Solution Overview
Problem
Current flash memory systems face challenges in reducing the size and cost of memory cell arrays while minimizing leakage currents and parasitic currents, which affect the efficiency of data reading and programming operations in three-dimensional memory arrays.
Innovation Solution
A three-dimensional memory architecture with variable resistive memory elements is implemented, featuring a single-sided word line architecture and a double-global-bit-line configuration, which reduces leakage currents and allows for efficient decoding of bit lines and word lines, enabling parallel access and operation of memory elements with reduced parasitic currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If diodes are connected in series with memory elements to reduce leakage currents, then leakage current is reduced, but device complexity increases
Solution Approach 1:
The patent removes the diode component from the memory element structure entirely. By extracting this unnecessary component, the invention simplifies the device architecture while maintaining the ability to manage leakage currents through the 3D array architecture itself, where vertical bit lines and word lines are selectively activated to access specific memory planes without requiring protective diodes.
Solution Approach 2:
The patent transitions from a planar 2D memory array to a three-dimensional stacked array of memory planes. This dimensional change allows multiple memory elements to share common bit and word lines vertically, reducing the overall number of lines and enabling leakage current management through spatial separation and selective activation of different memory planes, thereby eliminating the need for diodes.
2Quantity of substance
If multiple memory planes are stacked vertically to increase storage capacity, then data storage density is improved, but leakage current and parasitic current increase
Solution Approach 1:
The patent divides the memory array into multiple independent planes stacked vertically, with each plane accessible through dedicated word lines and bit lines. This segmentation allows selective activation of individual planes during read or program operations, preventing current leakage to unselected planes through proper voltage control and timing sequences that isolate active planes from inactive ones.
Solution Approach 2:
The patent employs preliminary voltage application and timing control sequences that prepare and activate specific word lines and bit lines before memory element access. By controlling the timing and sequence of voltage application to word lines and bit lines, the system ensures that only the intended memory elements are accessed while preventing parasitic currents from flowing through unselected paths in the stacked array.
3Area of stationary object
If a three-dimensional array architecture is used to reduce memory size, then area is reduced, but decoding complexity of bit lines and word lines increases
Solution Approach 1:
The patent implements a unified control architecture where word lines and bit lines serve multiple functions across different memory planes. The same physical lines are reused for addressing memory elements in various planes through temporal multiplexing and voltage control, reducing the total number of decoding lines required while maintaining efficient access to all memory elements in the three-dimensional array.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This architecture results in a highly scalable and efficient memory system with reduced leakage currents, lower power consumption, and improved data processing capabilities, enhancing the storage density and operational reliability of flash memory systems.
Implementation Method 1
memory elements which reversibly change a level of electrical conductance in response to a voltage difference being applied across them
Data Source
AI summary
A three-dimensional array of memory elements is formed across multiple layers of planes positioned at different distances above a semiconductor substrate. The memory elements reversibly change a level of electrical conductance in response to a voltage difference being applied across them. The three-dimensional array includes a two-dimensional array of pillar lines from the substrate through the multiple layers of planes. A first set of pillar lines acts as local bit lines for accessing the memory elements together with an array of word lines on each plane. A second set of pillar lines is connected to the word lines. An array of metal lines on the substrate is switchable connected to the pillar lines to provide access to the first and second sets of pillar lines, thereby to provide access respectively to the bit lines and word lines of the three-dimensional array.