3D Memory Array With Vertically Stacked Transistors
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Solution Overview
Problem
Current semiconductor memory technologies face challenges in achieving high density and reduced footprint while maintaining manufacturing ease, particularly in volatile and non-volatile memory applications.
Innovation Solution
A three-dimensional (3D) memory array architecture is developed with vertically stacked memory cells, each comprising a thin film transistor (TFT) with a word line as a gate electrode, bit line as a source/drain electrode, and source line as another source/drain electrode, utilizing an insulating memory film and oxide semiconductor channel region, allowing for reduced cell size and increased density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional planar memory architecture is used, then manufacturing process is simpler, but memory density and footprint are limited
Solution Approach 1:
The patent transitions from a two-dimensional planar memory architecture to a three-dimensional vertically stacked architecture. Multiple memory cells are stacked along the vertical direction, with each cell containing a ferroelectric capacitor and transistor. This dimensional change enables significantly higher memory density within the same footprint area while maintaining compatibility with standard semiconductor manufacturing processes through sequential deposition and patterning steps
2Area of moving object
If memory cell size is reduced to increase density, then footprint is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The memory cell is segmented into distinct functional components: a ferroelectric capacitor with separate top and bottom electrodes, a transistor with gate, source, and drain regions, and insulating layers. Each component is formed through dedicated deposition and patterning steps, allowing independent optimization of dimensions and tolerances. The capacitor uses thin ferroelectric films (e.g., Pb(Zr,Ti)O3 or Pb1-xLaxZr1-yTiyO3) with controlled thickness to achieve small area while maintaining manufacturing control through precise film deposition parameters
3Speed
If volatile memory technology is used, then write/read speed is fast, but data is lost when power is removed
Solution Approach 1:
The patent employs a composite material structure where a ferroelectric material (such as Pb(Zr,Ti)O3, Pb1-xLaxZr1-yTiyO3, or other lead-free alternatives) is integrated with standard semiconductor materials (silicon, metal interconnects, insulators). The ferroelectric layer exhibits both fast switching characteristics similar to volatile memory and non-volatile data retention due to its ability to maintain polarization states without power. This composite approach combines the speed advantage of volatile memory with the data retention capability of non-volatile memory in a single device structure
Data Source
AI summary
A device includes a semiconductor substrate; a first word line over the semiconductor substrate, the first word line providing a first gate electrode for a first transistor; and a second word line over the first word line. The second word line is insulated from the first word line by a first dielectric material, and the second word line providing a second gate electrode for a second transistor over the first transistor. The device further including a source line intersecting the first word line and the second word line; a bit line intersecting the first word line and the second word line; a memory film between the first word line and the source line; and a first semiconductor material between the memory film and the source line.