Digital Storage TRIZ Cases

A resistive memory device adjusts set and reset voltage levels using a temperature sensor to maintain stable write operations.

Mapping defective STT-MRAM cells to redundant bits enables real-time error correction without storing failure locations.

A semiconductor device latches data groups on separate input output lines to generate output signals based on burst length settings.

Dynamic back gate voltage control reduces leakage current and improves refresh characteristics by adjusting voltage based on operational states.

A threshold voltage compensated sense amplifier adjusts transistor drive strength via control signals to match specific memory operation requirements.

Segmenting signal amplification across dies with fine-pitch interconnections eliminates SERDES circuitry to boost throughput while lowering power consumption.

A refresh circuit uses a multiplexer to select self-refresh commands for specific memory banks.

Segmented voltage regulation compensates for process skew in 3D stacked dies, eliminating expensive binning requirements.

A sense amplifier array positions transistors between upper and lower mat bit lines to ensure adequate channel length.

Cross interconnection wiring buses synchronize multiple I/O driver modules to test x4 and x8 DUTs simultaneously without fixture changes.

A local amplifying circuit uses a precharge module to prepare data lines before read operations begin.

A three-dimensional memory array stacks transistors vertically to increase density while maintaining manufacturing precision.

Multiplexing command and data signals on shared terminals reduces pin counts, lowering testing costs and substrate space constraints.

Clock and power control circuitry reuse the chip enable signal to gate memory segments, reducing standby leakage without adding design complexity.

A 4CPP memory device uses fly shared bit lines to reduce electrical loading on the bit line structure.

Merging SRAM and shift registers into one magnetic nanowire reduces area occupancy and power consumption while maintaining data processing functionality.

Segmenting the magnetic layer into buffer and storage regions resolves manufacturing complexity while maintaining domain wall stability.

Precharging bit lines to half supply voltage reduces leakage current and improves data retention in eDRAM.

A memory integrated circuit uses separate command codes for high and low order address bits to expand storage capacity.

A pipe register circuit merges multiple data registers into a shared unit, reducing semiconductor memory area while minimizing data output delays.

Anti-fuse circuit electrically programs repair addresses from detection logic, resolving inefficiencies in external address input methods.

Reference voltage inversely proportional to temperature enables precise back bias detection, maintaining write recovery margins across thermal variations.

A memory input buffer circuit generates offset calibration codes before receiving mode register codes to adjust current elements for precise analog-to-digital conversion.

Checker circuit detects write disturbances in adjacent phase change memory cells and performs refresh operations to maintain data integrity.

Dual port memory updates data at clock frequency using a comparator to manage read-write cycles.

A memory device senses data values by measuring the time required for a resistance state to change under applied electric fields.

A memory controller delays command and address signals to determine the timing eye through repetitive activation and measurement.

A semiconductor memory device uses a clock input buffer and internal clock generator to manage signal states.

Connecting a secondary gate to the drain reduces current leakage across the channel, eliminating the need for large storage capacitors.

A DRAM circuit adjusts time margins by controlling delay sub-circuits based on calculated target delays.

Asymmetric dummy transistors counterbalance harmful coupling to maintain node voltage accuracy without sacrificing search speed.

Replacing dummy circuitry with a shared column select line improves manufacturing efficiency and space utilization while providing redundant fault tolerance.

A memory controller probabilistically adjusts the number of victim rows refreshed to mitigate data corruption in dynamic random access memory.

Composite DNA sequences with error correction modules maintain data integrity during biological storage, addressing high mutation rates in carrier cells.

A multi-level cell memory architecture senses voltages based on reference cells to increase storage density.

Calibrating termination resistance dynamically reduces power consumption while maintaining signal integrity during write operations.

Shunting transistors reduce bit line resistance in shared bit line SMT MRAM arrays, preventing program disturb effects in unselected columns.

A control logic circuit selectively activates sense amplifiers to form specific read current paths.

A refresh control circuit adjusts memory cell refresh rates based on detected error addresses to prevent data loss.

Shunting wordline ends to low voltage sources accelerates ON-OFF transitions, reducing latency in dense 3D memory stacks.

A semiconductor memory device uses stacked metallic conductive layers and insulating capping structures to enhance integration density.

A memory control unit selectively activates and refreshes adjacent word lines during target operations to maintain data integrity.

Digit line jumpers connect split access lines across sense amplifier regions to form extended paths.

Segmented write driver applies independent voltages to bit and source lines, reducing effective metal resistance and sub-threshold leakage current.

Replacing the bottom electrode with a silicon oxide conductive bridge filament concentrates Joule heating to lower reset current from 300 μA to under 100 μA.

A programmable dynamic port enable signal controls transmission gates in domino SRAM devices to prevent early data coupling.

A method adjusts voltage, current, and pulse width based on memory cell resistance to achieve tight resistance distribution.

Unified control logic and time-multiplexed shifters reduce signal lines in synchronous memory data output circuits, improving layout efficiency.

Precharging local data lines allows early read enable signals, eliminating timing errors and power waste.

ECC decoding detects bit errors in shrunk DRAM cells, allowing control logic to adjust sense amplifier voltages and increase operating margins.