Integrated Circuit Memory Power Control via Chip Enable Signal
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As process geometries decrease in integrated circuit memories, standby power consumption increases due to current leakage, and existing power gating methods require additional design and validation efforts from users to control power saving features effectively.
Innovation Solution
The integration of clock control and power control circuitry within integrated circuit memories, utilizing a chip enable signal to switch between operating and low power states, allowing transparent power gating without additional user design or validation efforts, by reusing the setup time associated with the chip enable signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If process geometries are decreased to increase memory density, then memory capacity is improved, but standby power consumption increases due to current leakage
Solution Approach 1:
The memory circuit is divided into multiple independently power-controllable segments or blocks. Each segment can be individually gated to enter low-power state, allowing selective power reduction without affecting the entire memory array. This segmentation enables fine-grained power management to reduce leakage while maintaining active segments.
Solution Approach 2:
The power gating mechanism is activated periodically based on memory access patterns. During idle periods between accesses, power gating is enabled to reduce standby consumption. During active access periods, power gating is disabled to maintain performance. This periodic activation aligns power state changes with actual memory usage.
2Loss of energy
If dedicated power gating enable inputs are added to control power saving features, then power consumption is reduced, but device complexity and design validation effort increase
Solution Approach 1:
The existing chip enable signal, which already controls memory access operations, is extended to also control power gating functionality. This single signal performs dual functions: enabling/disabling memory accesses and enabling/disabling power gating. By reusing an existing control signal for multiple purposes, the need for dedicated power gating inputs is eliminated, reducing complexity while maintaining power savings.
3Loss of energy
If power gating is activated during memory operations, then power consumption is reduced, but access speed and performance deteriorate
Solution Approach 1:
The power gating state is dynamically adjusted based on real-time memory access activity. The system continuously monitors whether the memory is being accessed and transitions between powered and low-power states accordingly. This dynamic adaptation ensures power gating is only active during idle periods, preventing any degradation of access speed during actual operations.
Solution Approach 2:
Power gating is activated in advance during the setup time period of the chip enable signal, before the actual memory access operation begins. This preliminary activation ensures that when the memory does need to access data, the power gating is already in the appropriate state, and no performance degradation occurs during the critical access window.
4Device complexity
If chip enable signal setup time is extended to accommodate power state switching, then power gating control is simplified, but access latency increases
Solution Approach 1:
The chip enable signal setup time is extended only partially - just enough to accommodate the power state switching requirement, rather than adding excessive time. This minimal extension provides sufficient time for power gating activation while keeping the increase in access latency to the absolute minimum necessary, balancing control simplicity with performance requirements.
Data Source
AI summary
An integrated circuit memory 10, 12 has clock control circuitry 36 responsive to a clock signal CLK and a chip enable signal CEN to generate control signals for controlling the integrated circuit memory 10 in response to the clock signal CLK when the chip enable signal CEN indicates that the integrated circuit memory 10, 12 is active. When the chip enable signal CEN indicates that the integrated circuit memory 10, 12 is disabled, then power control circuitry 38 serve to switch portions of the integrated circuit memory 10, 12, such as word line driver circuitry 24, sense amplifiers 22 and buffer circuitry 30, into a low power state from an operating state. When the chip enable signal CEN activates the integrated circuit memory 10, 12, the power control circuitry 38 switches these portions 24, 22, 30 which are in the low power state back to the operating state.