Dual Port Memory Data Update for RF Power Measurement
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Solution Overview
Problem
Current systems for measuring power CCDF curves in RF applications are inefficient, requiring long times to capture sufficient samples for accurate measurements, often missing high peak levels and resulting in inadequate data for system design, especially when dealing with low percentage exceedance requirements.
Innovation Solution
An apparatus and method utilizing a dual port memory with an Analog to Digital Converter (ADC) and an updating element to sample and update data at the same clock frequency, enabling frequency counts of input signal values, allowing for real-time data storage and processing, including a comparator to manage port operations and ensure accurate data updating without indeterminate results.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If samples are captured at high speed for a short time using current systems, then the data capture rate is improved, but the measurement accuracy deteriorates due to missing high peak levels and insufficient samples for low percentage exceedance requirements
Solution Approach 1:
The memory is divided into two separate ports (port 0 and port 1), allowing independent read and write operations to occur simultaneously on different ports. This segmentation enables the system to capture and process samples continuously without waiting for sequential read-write cycles, thereby maintaining high capture rates while ensuring sufficient sample accumulation for accurate low percentage exceedance measurements
Solution Approach 2:
The system pre-allocates and prepares the dual port memory structure before sampling begins, with port 0 configured for writing incoming samples and port 1 configured for reading processed data. This preliminary setup eliminates the need for sequential port switching during operation, ensuring continuous high-speed capture while maintaining measurement accuracy through adequate sample collection
2Device complexity
If sequential read-write operations are performed on a single port memory, then the device complexity is reduced, but the productivity deteriorates due to operating at half the clock frequency
Solution Approach 1:
The memory is divided into two separate ports (port 0 and port 1), allowing independent read and write operations to occur simultaneously on different ports. This segmentation enables the system to capture and process samples continuously without waiting for sequential read-write cycles, thereby maintaining high capture rates while ensuring sufficient sample accumulation for accurate low percentage exceedance measurements
Solution Approach 2:
While port 0 is writing incoming samples to memory, port 1 simultaneously reads previously written data for processing. This continuous parallel operation eliminates idle time between read and write operations, maintaining productivity at full clock frequency rather than half frequency, while the memory structure remains relatively simple with only two ports
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables fast and accurate measurement of RF signal power characteristics, capturing tens of millions of samples per second without gaps, significantly reducing measurement time and improving data accuracy for CCDF curve generation, especially for low percentage exceedance measurements.
Implementation Method 1
an Analog to Digital Converter (ADC) having an input for receiving the input signal and an output, the ADC sampling the input signal at sampling points to provide a parameter value corresponding to a desired parameter of the input signal at each sampled point
Implementation Method 2
a dual port memory for storing data relating to each received parameter value, the memory having an input for receiving each parameter value and an output for providing the stored data from an address in the memory corresponding to the received parameter value
Implementation Method 3
an updating element having an input coupled to the output of the memory for receiving the stored data, for updating that stored data and for providing the updated data at an output coupled to an input of the dual port memory for writing back into the address corresponding to the received parameter value
Implementation Method 4
a comparator having a first input coupled to the output of the ADC for receiving the parameter value on the first clock cycle of the dual port memory and a second input for receiving a next received parameter value on a second clock cycle and an output for providing a match signal if the received parameter value and the next received parameter value are the same
Data Source
AI summary
A dual port memory is updated at substantially the same data sampling rate as a clock frequency of the dual port memory. The dual port memory stores data relating to each different parameter value in a stream of data samples, and provides the stored data from an address in the memory corresponding to the received parameter value. An updating element updates stored data and provides the updated data to an input of the dual port memory for writing back into the address corresponding to the received parameter value. A first port of the dual port memory is utilised as the output of the dual port memory coupled to the input of the updating element on a first clock cycle of the dual port memory, and a second port of the dual port memory is normally utilised as the input of the dual port memory coupled to the output of the updating element on a second clock cycle, the next address being accessed via the first port on the second clock cycle. A comparator receives the parameter value on the first clock cycle of the dual port memory and a next received parameter value on a second clock cycle, and provides a match signal if the received parameter value and the next received parameter value are the same. The match signal is utilised to enable the first port of the dual port memory to be used as the input for the second clock cycle so that the data updated by the updating element on the first clock cycle is provided at the first port rather than the second port and is therefore correctly provided to the input of the updating element on the second clock cycle.