Back Gate Driver for Memory Cell Leakage Reduction
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Solution Overview
Problem
Existing memory devices face challenges in reducing leakage current and improving refresh characteristics, particularly due to fluctuations in the back gate voltage affecting the threshold voltage of memory cells.
Innovation Solution
The memory device incorporates a back gate driver that adjusts the voltage level of the back gate voltage from a first level to a second level during an active period when a selected word line is enabled, thereby reducing leakage current and improving refresh characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the back gate voltage is maintained at a constant level, then the structure is simple and easy to control, but the leakage current cannot be reduced and refresh characteristics are not improved
Solution Approach 1:
The back gate voltage is changed from a static constant level to a dynamic variable level that changes based on the operational state. Specifically, the back gate voltage is lowered during the active period when the word line is enabled, and restored to the original level during the precharge period. This dynamic adjustment allows the system to reduce leakage current when needed while maintaining simplicity in other periods.
Solution Approach 2:
The voltage parameter of the back gate is changed from a fixed value to a variable value that depends on the operational period. The back gate voltage driver circuit adjusts the voltage level based on whether the memory device is in precharge or active period, enabling optimal performance for each phase without requiring complex continuous control mechanisms.
2Reliability
If the back gate voltage is adjusted dynamically, then leakage current is reduced and refresh characteristics are improved, but the control complexity increases
Solution Approach 1:
The back gate voltage driver circuit automatically adjusts the back gate voltage based on the operational state without requiring external intervention. The circuit detects whether the memory device is in precharge or active period and autonomously sets the appropriate voltage level, simplifying the overall control architecture while achieving dynamic voltage adjustment.
Solution Approach 2:
The back gate voltage driver circuit uses feedback from the operational state (precharge or active period) to automatically adjust the back gate voltage. This feedback mechanism ensures that the voltage is optimized for the current operational phase, improving refresh characteristics while maintaining controlled complexity through state-dependent voltage adjustment.
3Power
If a higher word line driving voltage is applied during active period, then the selected word line can be enabled effectively, but voltage fluctuations affect adjacent word lines and cause threshold voltage changes in memory cells
Solution Approach 1:
The back gate voltage adjustment is applied locally to the back gate line corresponding to the selected word line, rather than uniformly across all back gate lines. This localized adjustment allows the system to handle the voltage fluctuations caused by high word line driving voltage specifically where needed, reducing threshold voltage changes in affected memory cells while maintaining overall system performance.
Data Source
AI summary
Memory devices and methods of operating thereof. A memory device may include a plurality of memory cells each including a cell transistor having a back gate that is shared with a cell transistor of an adjacent memory cell through a back gate line, a forward gate that is connected to a corresponding word line, and a cell capacitor that is connected to a first electrode of the cell transistor; a sub-word line driver configured to apply a word line driving voltage to a selected word line; a back gate driver configured to change a back gate voltage applied to the back gate line from a first voltage level to a second voltage level during an active period in which the selected word line is enabled; and a sense amplifier configured to sense data through bit lines connected to second electrodes of the cell transistors of the plurality of memory cells.