Phase Change Memory Checker Circuit for Write Disturbance
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Solution Overview
Problem
Phase change memory devices experience disturbances in adjacent memory cells due to heat transfer during programming operations, leading to unintended changes in resistance values and data integrity issues.
Innovation Solution
A semiconductor memory device with a checker circuit that performs a check read operation on adjacent memory cells to detect write disturbances, and performs a refresh operation to maintain data integrity, thereby improving reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a write operation is performed on memory cells, then data can be programmed into the memory cell array, but heat is generated that may cause unintended set or reset operations in adjacent memory cells
Solution Approach 1:
The patent applies preliminary action by performing a check read operation on adjacent memory cells immediately after the write operation to detect potential disturbances before they affect data integrity. The controller proactively checks the state of adjacent cells to identify and correct disturbances caused by heat transfer during programming operations.
2Productivity
If repetitive read operations are performed on one or more rows of memory cells, then data can be retrieved, but neighboring rows of memory cells may experience undesired disturbance
Solution Approach 1:
The patent applies preliminary action by performing check read operations on adjacent rows after read operations on target rows. This detects disturbances caused by repetitive reading before they propagate to neighboring rows, allowing for timely correction and prevention of data corruption.
Solution Approach 2:
The patent implements feedback by using the checker circuit to continuously monitor the state of memory cells and provide information back to the controller. When disturbances are detected in adjacent cells during read operations, the controller receives feedback and can perform corrective actions to maintain data integrity.
3Reliability
If a checker circuit is added to detect write disturbances, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent applies universality by designing the checker circuit to serve multiple functions: detecting disturbances from write operations, detecting disturbances from read operations, and providing feedback for correction. This multi-functional approach improves reliability without proportionally increasing complexity, as a single circuit structure handles multiple detection tasks.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively detects and corrects write disturbances, enhancing the reliability of phase change memory devices by ensuring accurate data storage and retrieval.
Implementation Method 1
When a phase change memory performs a set operation or a reset operation on its phase change memory cells, heat is generated at the corresponding phase change memory cells
Implementation Method 2
Some nonvolatile memories, phase like change memories, are configured to change resistance values of its memory cells through a heating process
Implementation Method 3
The heat generated at the phase change memory cells may have an undesired influence other phase change memory cells adjacent to those being programmed
Data Source
AI summary
Nonvolatile memory devices, such as phase change memory (PCM) devices or other resistance based memory devices, are disclosed as well as methods of operating the same. Resistance states of the memory cells may be altered due to write disturbance resulting from write operations to neighboring word lines. Data reliability may be increased by performing check read operations of neighboring memory cells in response to a write operation. In some examples, a number of consecutive write operations performed on a memory cell array or a portion thereof is monitored. When the number of consecutive write operations reaches a predetermined number, which may be a randomly generated number in some examples, a corresponding check read operation may be performed. If the check read operation indicates certain sections of the memory have been subject to a write disturbance, data in such sections may be refreshed to provide adjust resistance states of corresponding memory cells. Monitoring for write disturbance and performing corresponding refresh operations may be performed by the nonvolatile memory semiconductor chip and/or by external devices, such as a controller.