Synchronous Memory Data Output Circuit Signal Line Reduction
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Solution Overview
Problem
Conventional data output circuits in synchronous memory devices require a large number of signal lines for control, leading to inefficient layout in highly integrated memory devices due to the use of independent signals for each pipelatch, which affects layout efficiency.
Innovation Solution
A data output circuit with a plurality of pipelatches that share control signals and a pre-driver, utilizing data switching sections, selection sections, and shifters to alternate and delay data output based on a starting column address and data output mode, reducing the number of control signal lines needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If independent control signals are used for each pipelatch, then data output sequencing is achieved, but the number of signal lines increases leading to poor layout efficiency
Solution Approach 1:
The patent combines multiple independent control signals into shared control signals that are commonly applied to multiple pipelatches. Specifically, the enable signals PIN1-PIN4 and control signals ctr1-ctr4 are generated through a unified control logic that processes the column address and burst type information, allowing all pipelatches to be controlled by a reduced set of common control lines rather than requiring separate independent control signals for each pipelatch.
Solution Approach 2:
The control logic unit is designed to universally generate control signals that can be applied to multiple pipelatches regardless of their individual data output requirements. The shared control signals serve multiple functions: they enable different pipelatches at appropriate times, control data switching between different output paths, and coordinate the operation of data selection sections and shifters across all pipelatches using a single set of control lines.
2Manufacturing precision
If more signal lines are used for control, then precise data output control is achieved, but layout area increases
Solution Approach 1:
The patent introduces temporal dimension to the control signal generation by using time-multiplexed control. The control logic generates enable signals and control signals at different time points based on the clock phase and burst type, allowing precise control of data output sequencing through time-based differentiation rather than requiring separate spatial signal lines. The shift registers further utilize temporal dimension by delaying signals by half clock periods to achieve precise timing control.
Solution Approach 2:
The control logic changes the parameters of the control signals dynamically based on the input conditions (column address lower 2 bits and burst type). The same physical control signal lines carry different signal values and timing characteristics depending on the operational mode, allowing precise control adaptation without increasing the number of signal lines. The control signals are modified in terms of their temporal characteristics (timing, duration, phase) rather than requiring additional spatial channels.
Data Source
AI summary
A data output circuit of a synchronous memory device including a plurality of pipelatches having an N bits prefetch function. Each pipelatch comprises a data switching section for switching an output path of N bits data; a first data selection section for receiving one half of the N bits data and outputting the one half in response to a first control signal; a second data selection section for receiving the other half of the N bits data and outputting the other half in response to the first control signal; a first shifter for outputting a second control signal delayed by a first time after receiving the first control signal; and a second shifter for receiving the data outputted from the second data selection section and outputting the data with a delay of the first time in response to the second control signal.