DRAM Refresh Circuit Bank Segmentation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Volatile memory devices, such as DRAM, require frequent refresh operations to maintain data integrity, leading to inefficiencies in memory cell array utilization as not all memory banks can be refreshed simultaneously without disrupting normal operations.
Innovation Solution
A refresh circuit and method that utilize a mode register, refresh controller, and multiplexer circuit to selectively perform refresh operations on one memory bank group while allowing other groups to operate normally, using self-refresh commands and oscillation signals to generate row active and address signals, enabling efficient data retention and utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If refresh operations are performed on all memory banks simultaneously, then data retention is ensured, but memory cell array utilization efficiency decreases
Solution Approach 1:
The memory banks are divided into multiple groups, and refresh operations are performed on one group at a time while other groups continue normal operations. This segmentation allows partial refresh without halting entire memory array, resolving the contradiction between ensuring data retention and maintaining utilization efficiency.
Solution Approach 2:
Refresh operations are performed periodically on different memory bank groups in a round-robin fashion. Each group undergoes refresh at predetermined intervals while other groups are active, ensuring all banks are refreshed over time without simultaneous operation, thus balancing reliability and productivity.
2Reliability
If refresh operations are performed on one memory bank group, then that group's data is retained, but other groups cannot be refreshed simultaneously
Solution Approach 1:
While one memory bank group undergoes refresh, other groups continue normal read/write operations without interruption. This continuity ensures that the memory system remains productive throughout the refresh cycle, reducing the effective loss of time for the overall system while maintaining data retention for refreshed banks.
Solution Approach 2:
The system proactively manages refresh scheduling by pre-dividing memory banks into groups and establishing a round-robin refresh pattern. This preliminary organization allows seamless transition between groups, ensuring continuous operation and minimizing idle time without compromising data retention.
3Reliability
If all memory banks undergo refresh operation, then data integrity is maintained, but operating speed decreases
Solution Approach 1:
Memory banks are segmented into multiple groups that are refreshed sequentially rather than simultaneously. This segmentation allows other groups to operate at full speed during refresh of one group, maintaining overall system operating speed while ensuring data integrity through periodic refresh of all banks.
Solution Approach 2:
Instead of refreshing all memory banks at once, the system performs partial refresh on one group at a time. This partial action approach maintains data integrity for refreshed banks while allowing other banks to continue high-speed operations, thus preserving overall operating speed.
Data Source
AI summary
A refresh circuit and a semiconductor memory device including the refresh circuit are disclosed. The refresh circuit includes a mode register, a refresh controller and a multiplexer circuit. The mode register generates a mode register signal having information relating to a memory bank on which a refresh operation is to be performed. The refresh controller generates a self-refresh active command and a self-refresh address based on a self-refresh command and an oscillation signal. The multiplexer circuit may include a plurality of multiplexers. Each of the multiplexers selects one of an active command and the self-refresh active command in response to bits of the mode register signal. Each of the multiplexers generates a row active signal based on the selected command, and selects one of an external address and the self-refresh address to generate a row address.