Memory Device Pin Count Reduction via CMD/IO Multiplexing
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Solution Overview
Problem
High pin counts in integrated circuit memory devices and testers lead to increased costs and complexity in testing, as well as space constraints on semiconductor substrates, limiting the ability to test multiple devices efficiently.
Innovation Solution
A multiplexing system that reduces the pin count by using a CMD/IO multiplexer with eight externally accessible IO terminals, a CMD/IO control signal, and a clock signal to connect IO and command signals internally, allowing simultaneous testing of multiple memory devices with shared signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of bonding pads and pins is increased to support higher integration levels, then the functionality and capacity of memory devices are improved, but the pin count increases leading to higher testing costs and reduced testing efficiency
Solution Approach 1:
The patent combines command signals and I/O signals onto the same physical pins, allowing a single pin to carry multiple types of signals at different times. This merging approach reduces the total number of pins required while maintaining full functionality for both command and data operations.
Solution Approach 2:
The patent employs dynamic signal multiplexing where pins switch between carrying command signals and I/O signals based on timing control. This dynamic allocation allows the same physical pin to serve multiple functions sequentially, reducing static pin requirements.
2Productivity
If more pins are used to connect memory devices to testers, then more signals can be transmitted simultaneously, but the ability to test multiple devices simultaneously is reduced due to tester terminal limitations
Solution Approach 1:
The patent makes each pin universal by enabling it to carry both command signals and I/O signals depending on the operational phase. This multi-functionality allows the same pin to participate in different signal types, enabling multiple devices to share tester terminals efficiently.
Solution Approach 2:
The patent uses periodic time-division multiplexing where command signals and I/O signals are transmitted in alternating time slots through the same pins. This periodic switching allows multiple devices to be tested simultaneously by coordinating their signal phases.
3Reliability
If traditional separate command and I/O terminals are used, then signal integrity is maintained, but space constraints on semiconductor substrates are exacerbated
Solution Approach 1:
The patent merges command and I/O signal paths onto shared physical pins, reducing the number of separate terminal connections required on the substrate. This consolidation frees up substrate space while maintaining signal integrity through controlled switching mechanisms.
Data Source
AI summary
Methods, memory devices and systems are disclosed. In one embodiment, a non-volatile memory device receives command signals through the same input/output terminals that receive address signals and write data signals and transmit read data signals. The input/output terminals are connected to a multiplexer, which is responsive to a received mode control signal to couple the input/output terminals to either a command bus or an input/output bus. A latch in the memory device latches the command signals when the mode control signal causes the input/output terminals to be coupled to the input/output bus. As a result, the command signals continue to be applied to the command bus. When the mode control signal causes the input/output terminals to be coupled to the input/output bus, write data signals are clocked into the memory device and read data signals are clocked out of the memory device responsive to a received clock signal.