Sense Amplifier Voltage Adjustment for DRAM Error Patterns
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Solution Overview
Problem
The increasing bit errors and decreasing yield of dynamic random access memories (DRAMs) due to shrinking fabrication design rules necessitate a solution to enhance the performance and reliability of semiconductor memory devices.
Innovation Solution
A semiconductor memory device incorporating a memory cell array, sense amplifiers, an error correction code (ECC) engine, and a control logic circuit that adjusts voltage levels based on error pattern information to increase the operating margin of sense amplifiers, thereby improving data sensing and restoration accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If fabrication design rules are shrunk to increase storage density, then storage density is improved, but bit error rate increases and yield decreases
Solution Approach 1:
The system performs preliminary ECC decoding and error pattern detection on read data before using this information to adjust sense amplifier voltages for subsequent read operations. This preliminary analysis allows the system to proactively compensate for identified error patterns, reducing bit errors in future operations while maintaining high storage density from shrunk fabrication rules
Solution Approach 2:
The system dynamically changes the voltage parameters of sense amplifiers based on detected error patterns. By adjusting voltage levels according to specific error patterns identified through ECC decoding, the system compensates for manufacturing variations and shrinkage effects, thereby reducing bit errors while maintaining improved storage density
2Quantity of substance
If fabrication design rules are shrunk to increase storage density, then storage density is improved, but manufacturing yield decreases
Solution Approach 1:
The system implements feedback by continuously monitoring error patterns through ECC decoding and using this information to adjust sense amplifier voltages. This closed-loop feedback mechanism compensates for manufacturing variations introduced by shrunk design rules, improving yield by reducing the impact of process variations on device performance
Solution Approach 2:
The system performs preliminary error pattern analysis through ECC decoding to identify manufacturing defects and variations before they affect subsequent operations. This preliminary detection allows for proactive voltage adjustments that compensate for manufacturing yield issues while maintaining high storage density
3Reliability
If voltage levels are adjusted based on error pattern information, then operating margin and data reliability are improved, but device complexity increases
Solution Approach 1:
The system performs self-adjustment by automatically detecting error patterns through its own ECC decoding functionality and using this information to adjust its sense amplifier voltages without external intervention. This self-service approach improves data reliability while minimizing the need for additional complex external control logic
Solution Approach 2:
The ECC decoding unit serves multiple functions: it not only corrects errors but also identifies error patterns that inform voltage adjustments. This multi-functionality allows the system to improve data reliability through a single integrated component rather than requiring separate dedicated control logic, thereby reducing overall device complexity
Data Source
AI summary
A semiconductor memory device includes a memory cell array, an ECC engine, a voltage generator and a control logic circuit. The memory cell array includes a plurality of memory cells coupled to word-lines and bit-lines, and a plurality of sense amplifiers to sense data stored in the plurality of memory cells. The ECC engine reads memory data from a target page of the memory cell array, performs an ECC decoding on the memory data, detects, based on the ECC decoding, an error in the memory data, and outputs error information associated with the error. The voltage generator provides driving voltages to the plurality of sense amplifiers, respectively. The control logic circuit controls the ECC engine, and controls the at least one voltage generator to increase an operating margin of each of the plurality of sense amplifiers based on error pattern information including the error information.