Semiconductor Memory Sense Amplifier Noise Control
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Solution Overview
Problem
Current semiconductor memory devices face challenges in efficiently controlling and reading data due to the simultaneous operation of multiple sense amplifiers, which can lead to noise and read operation errors, especially when trying to measure individual cell read currents or reference currents without increasing address signals.
Innovation Solution
The semiconductor memory device incorporates a control logic circuit that allows for selective operation of sense amplifiers based on write data, enabling the formation of read current paths to specific memory or reference cells, thereby allowing for individual current measurement and reducing noise influences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple sense amplifiers operate simultaneously to increase read throughput, then productivity is improved, but noise increases and read operation accuracy deteriorates
Solution Approach 1:
The patent implements dynamic control of sense amplifier operation by introducing a control logic circuit that selectively activates sense amplifiers based on write data patterns. This dynamic activation/deactivation mechanism allows the system to adapt the number of operating sense amplifiers to the specific read operation requirements, thereby maintaining read accuracy while optimizing throughput for different data patterns.
Solution Approach 2:
The patent divides the sense amplifier array into multiple independently controllable groups or units. The control logic circuit can selectively activate specific sense amplifiers based on the read operation requirements, allowing parallel operation of multiple sense amplifiers when needed while preventing simultaneous operation that would cause noise interference, thus resolving the contradiction between throughput and accuracy.
2Measurement precision
If individual cell read currents are measured to improve measurement precision, then measurement precision is improved, but device complexity increases due to additional control circuitry
Solution Approach 1:
The control logic circuit performs multiple functions: it decodes write data to determine which sense amplifiers should be active, generates appropriate control signals for selective sense amplifier activation, and coordinates the timing of read operations. By consolidating these control functions into a single multi-functional circuit, the patent achieves precise current measurement without proportionally increasing overall device complexity.
Solution Approach 2:
The control logic circuit utilizes the existing write data signals already present in the memory system to automatically determine which sense amplifiers should be activated for the current read operation. This self-service approach eliminates the need for separate address signals or additional control inputs, thereby achieving precise current measurement while minimizing the increase in device complexity.
3Speed
If the number of sense amplifiers is increased to improve read speed, then speed is improved, but noise increases and measurement precision deteriorates
Solution Approach 1:
The patent implements dynamic control of sense amplifier operation by introducing a control logic circuit that selectively activates sense amplifiers based on write data patterns. This dynamic activation/deactivation mechanism allows the system to adapt the number of operating sense amplifiers to the specific read operation requirements, thereby maintaining read accuracy while optimizing throughput for different data patterns.
Solution Approach 2:
The patent changes the operational parameter of sense amplifier activation state from static (all amplifiers always on) to dynamic (selective activation based on data patterns). By changing this parameter, the system can optimize the balance between read speed and measurement precision, activating multiple amplifiers for speed when data patterns allow, and reducing active amplifiers for precision when needed.
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes a cell array including a plurality of memory cells, a reference circuit, a sense amplifier for sensing a read current flowing through the memory cell, and a reference current flowing through the reference circuit, a write driver for writing data to the memory cell, a sub cell area including the cell array, the sense amplifier, and the write driver, a memory area including a plurality of sub cell areas, and a control circuit for supplying first write data to the sub cell area including the sense amplifier which performs a first read operation of supplying the read current to a selected memory cell without supplying the reference current.