Refresh Controller for Dynamic Error-Based Memory Refresh
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Solution Overview
Problem
Semiconductor devices, such as DRAMs, face challenges in effectively verifying and correcting user data errors, particularly in managing error rates and refreshing cycles, which can lead to increased error frequencies and current consumption.
Innovation Solution
The semiconductor device incorporates a memory cell array for user data and error correction information, with a refresh control circuit that adjusts refreshing frequencies based on error detection, using a comparison circuit to identify and prioritize memory cells with errors, thereby increasing their refresh rate and preventing additional errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If the refresh cycle is increased to reduce current consumption, then power usage decreases, but the error rate of memory cells increases
Solution Approach 1:
The patent applies local quality by differentiating refresh operations between normal memory cells and cells with undetected errors. The refresh controller identifies specific memory cells that require enhanced refresh attention and applies a shorter refresh cycle only to those cells, while maintaining the longer refresh cycle for normal cells. This localized approach reduces overall current consumption while ensuring reliable error correction for problematic cells.
Solution Approach 2:
The refresh cycle is made dynamic rather than static. The refresh controller continuously monitors error rates and adjusts the refresh cycle length based on detected error conditions. When errors are detected, the system dynamically shortens the refresh cycle for affected cells; when no errors are present, it extends the refresh cycle to reduce power consumption. This dynamic adaptation resolves the contradiction between power savings and error rate control.
2Reliability
If the refresh cycle is decreased to reduce error rate, then reliability improves, but current consumption increases
Solution Approach 1:
Instead of applying a uniformly short refresh cycle to all memory cells, the patent selectively applies enhanced refresh only to specific cells that have exhibited errors. This localized refresh strategy maintains high reliability for problematic cells while avoiding the excessive current consumption that would result from refreshing all cells at high frequency.
Solution Approach 2:
The system applies partial refresh action only where necessary. Rather than excessively refreshing all memory cells, it performs targeted refresh operations on cells with undetected errors, using the error correction information to identify precisely which cells need attention. This partial action achieves sufficient reliability without the current consumption penalty of comprehensive high-frequency refreshing.
3Reliability
If error correction information is continuously monitored and refresh operations are adjusted accordingly, then error correction efficiency improves, but device complexity increases
Solution Approach 1:
The refresh control system uses the error correction information generated during normal read operations to automatically identify and refresh problematic cells. The system serves itself by leveraging existing error correction data rather than requiring separate monitoring mechanisms. This self-service approach improves error correction efficiency while minimizing additional device complexity.
Solution Approach 2:
The error correction information serves multiple functions: it corrects read errors and simultaneously identifies memory cells requiring enhanced refresh attention. The refresh controller reuses the same error correction data for both correction and refresh scheduling purposes, eliminating the need for separate monitoring systems and reducing overall device complexity while maintaining high error correction efficiency.
Data Source
AI summary
A device includes a plurality of memory cells, an error detection circuit configured to detect at least one memory cell storing error data and a refresh control circuit including a register configured to store an error address corresponding to the at least one memory cell storing error data. The refresh control circuit is configured to control a refresh cycle of the error address.