DRAM Transistor Secondary Gate Leakage Control
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Solution Overview
Problem
Conventional DRAM designs require frequent refresh due to current leakage across the channel in the OFF state of the transistor, leading to inefficient storage and low integration due to the need for large capacitors, which results in an incompact structure and reduced integration.
Innovation Solution
The introduction of a secondary gate connected to the drain, which provides supplementary control to the semiconductor layer and acts as a negative bias during reading, combined with a capacitor storage structure between the secondary gate and a first electrode, optimizing the transistor performance and reducing current leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional DRAM design with single gate control is used, then device structure is simple, but current leakage across channel in OFF state occurs frequently requiring frequent refresh
Solution Approach 1:
The gate control function is segmented into two independent gates: a primary gate connected to word lines for main control, and a secondary gate connected to drain for supplementary control. This segmentation allows independent optimization of each gate's function, enabling better leakage control through coordinated operation while maintaining manageable structural complexity through modular design
Solution Approach 2:
The secondary gate acts as an intermediary element between the drain and the semiconductor layer, providing additional control potential that modulates the channel conductivity. This intermediary gate enables fine-tuned control of current leakage by applying appropriate voltages to adjust the energy barrier at the channel, supplementing the primary gate's control capability
2Reliability
If large capacitor is used for storage, then data retention is improved, but integration is reduced and structure becomes incompact
Solution Approach 1:
The secondary gate is merged with the drain structure and electrically connected to it, eliminating the need for separate capacitor components. The drain itself serves dual functions: as the electrical connection point and as part of the storage mechanism through the secondary gate control, achieving compact integration while maintaining data retention capability
Solution Approach 2:
The drain structure is given multi-functionality by serving both as the electrical connection element and as part of the storage control mechanism through the secondary gate. This universal element performs multiple roles (current path, storage control, potential barrier formation) that would traditionally require separate components, thereby improving integration density
3Reliability
If additional capacitor devices are used for storage, then storage capability is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The storage function is merged into the existing transistor structure by utilizing the secondary gate and drain combination, eliminating the need for separate capacitor fabrication processes. This integration reduces the number of manufacturing steps, materials required, and process complexity while achieving equivalent or improved storage capability
Solution Approach 2:
The transistor structure is designed to perform both switching and storage functions through the dual-gate configuration. The secondary gate connected to drain enables the transistor to maintain stored data through controlled leakage suppression, making the transistor a universal element that combines logic and memory functions, thereby simplifying manufacturing
Data Source
AI summary
A memory comprises a substrate, and word lines, bit lines and memory cells located on one side of the substrate. Each of the memory cells comprises a transistor comprising: a semiconductor layer comprising a source contact region, a channel region and a drain contact region connected sequentially; a primary gate electrically connected to one of the word lines; a source electrically connected to one of the bit lines and the source contact region of the semiconductor layer, respectively; a drain electrically connected to the drain contact region of the semiconductor layer; and a secondary gate electrically connected to the drain, wherein an orthographic projection of the primary gate on the substrate and an orthographic projection of the secondary gate on the substrate are at least partially overlapped with an orthographic projection of the channel region of the semiconductor layer on the substrate, respectively.