Programmable Port Enable Signal for SRAM Output Latch Protection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In domino Static Random Access Memory (SRAM) devices, early array outputs can corrupt the output latch contents or cause power increases, leading to hold time problems and latch corruption, which existing solutions fail to fully prevent through port enable signals or read enable signals.
Innovation Solution
A programmable dynamic port enable signal is generated using independently programmable leading and trailing edge clock signal derivations and a static input enable signal, preventing early memory array data from being coupled to the output node by controlling a transmission gate between the array output and the output latch.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a port enable signal is used to gate the array output to the output latch, then latch corruption is prevented, but the signal timing must be precisely controlled to avoid early data corruption
Solution Approach 1:
The port enable signal generation is segmented into two independent programmable delay circuits: one controlling the leading edge and another controlling the trailing edge of the signal. This segmentation allows precise independent adjustment of signal timing parameters to match specific memory access patterns while maintaining latch protection.
Solution Approach 2:
The port enable signal timing is made dynamic and programmable rather than fixed. The delay circuits allow the signal edges to be adjusted based on operating conditions, enabling the system to adapt to varying memory access speeds and patterns while maintaining reliable latch gating.
2Reliability
If the port enable signal timing is extended to prevent early data corruption, then latch corruption is avoided, but the sample time for valid data is reduced
Solution Approach 1:
The timing parameters of the port enable signal (leading edge delay and trailing edge delay) are made programmable, allowing optimization of the balance between protection duration and valid data sampling window. This enables adaptation to different memory access patterns without sacrificing either reliability or speed.
Solution Approach 2:
The signal timing characteristics are made dynamically adjustable through programmable delay circuits, allowing the system to optimize the port enable window based on actual memory access patterns, thereby maximizing both protection and sampling efficiency.
3Manufacturing precision
If independently programmable leading and trailing edge clock signal derivations are used, then precise signal timing control is achieved, but the circuit complexity increases
Solution Approach 1:
The signal generation circuit is segmented into two independent programmable delay blocks, each handling one edge of the clock signal. This modular segmentation achieves precise timing control for each edge independently while maintaining manageable circuit complexity through reuse of similar circuit structures.
Solution Approach 2:
The programmable delay circuit blocks are designed as universal, reusable modules that can be configured for different timing requirements. The same basic delay circuit structure serves multiple timing adjustment purposes, reducing overall design complexity despite the need for precise timing control.
Data Source
AI summary
A method of generating a dynamic port enable signal for gating memory array data to an output node includes generating a programmable leading edge clock signal derivation of an input dynamic clock signal; generating a programmable trailing edge clock signal derivation of the input dynamic clock signal, wherein the leading edge clock signal derivation and the trailing edge clock signal derivation are independently programmable with respect to one another; and gating the generated programmable leading and trailing edge clock signal derivations with a static input enable signal so as to generate the port enable signal such that, when inactive, the port enable signal prevents early memory array data from being coupled to the output node.