Semiconductor Memory Clock Buffer Control for Standby Current Reduction
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Solution Overview
Problem
Semiconductor memory devices consume excessive standby current in power-down mode, which is not efficiently managed by existing technologies.
Innovation Solution
A semiconductor memory device with a clock input buffer and internal clock generator that are controlled by specific control signals to buffer and divide clock signals, allowing the device to switch between normal and power-down modes while minimizing standby current consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the clock input buffer and internal clock generator are continuously operated to ensure stable clock signal generation, then the reliability of the memory device is improved, but the standby current consumption increases
Solution Approach 1:
The patent applies dynamics by making the clock input buffer and internal clock generator operable in different states (on/off) depending on the operating mode. The clock input buffer is turned on during normal operation and turned off during power-down mode, while the internal clock generator is activated only when needed. This dynamic switching of operational states allows the system to adapt between reliability and energy consumption requirements.
Solution Approach 2:
The internal clock generator is activated periodically or on-demand based on the operating mode rather than continuously. During power-down mode, the generator remains off to save power, and is activated only when a mode change is detected or when clock signals are needed. This periodic/on-demand activation pattern reduces standby current while maintaining functionality when required.
2Loss of energy
If the clock input buffer is turned off during power-down mode to reduce standby current, then the energy efficiency is improved, but the ability to quickly resume normal operation deteriorates
Solution Approach 1:
The patent applies preliminary action by detecting the power-down mode in advance and proactively turning off the clock input buffer before the mode change is fully executed. This allows the system to prepare for low-power operation ahead of time, reducing standby current consumption. The controller monitors operating modes and activates the buffer shutdown sequence early in the power-down transition.
Solution Approach 2:
The system uses feedback by having the controller continuously monitor the operating mode status and adjust the clock input buffer operation accordingly. When power-down mode is detected, the controller provides feedback to turn off the buffer; when normal mode is detected, the controller activates the buffer again. This closed-loop feedback mechanism ensures the buffer state always matches the required operating mode.
3Use of energy by moving object
If the internal clock generator is activated in response to chip selection signal to reduce power consumption, then the energy efficiency is improved, but the complexity of control logic increases
Solution Approach 1:
The chip selection signal serves multiple functions: it activates the internal clock generator, triggers mode changes, and coordinates with the clock input buffer operation. By making the chip selection signal multi-functional, the patent avoids adding separate control signals or complex control logic, thereby reducing overall device complexity while still achieving power savings through selective clock generator activation.
Data Source
AI summary
A semiconductor memory device has a clock input buffer that is turned ‘on’ or ‘off’ in response to a first control signal. The clock input buffer is configured to buffer an external clock signal in order to output a buffered clock signal. The memory device further includes an internal clock generator that is configured to generate an internal clock signal in response to the buffered clock signal. The generation of the internal clock signal is started in response to a second control signal.