Local Amplifier Circuit Precharge for Memory Readout Timing

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Solution Overview

Problem

In memory data readout, the time interval between the column selection signal and the read enable signal affects performance, leading to readout errors and unnecessary power consumption when the read enable signal is provided before data is fully transferred to the local data line.

Innovation Solution

A local amplifier circuit design that includes write control transistors, column selection transistors, PMOS transistors, and a precharge circuit to precharge local data lines to a high level, allowing the read control transistors to pull up or down levels based on a read enable signal, thereby shortening the time interval between the column selection and read enable signals.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If the read enable signal is provided early to shorten the time interval, then the memory performance is improved, but readout errors occur and power consumption increases

Engineering Contradiction:
Improvetime interval between column selection signal and read enable signalVSAvoidreadout accuracy
Core Design Contradiction:
Loss of timeVSReliability

Solution Approach 1:

The local data lines are precharged to a high level before the read operation begins. This preliminary action prepares the circuit state in advance, allowing the read enable signal to be provided earlier without causing readout errors, as the lines are already in the correct initial state regardless of when data transfer completes

Inventive Principle:
Principle #10Preliminary action

2Loss of time

If the read enable signal is provided early to shorten the time interval, then the memory performance is improved, but unnecessary power consumption occurs

Engineering Contradiction:
Improvetime interval between column selection signal and read enable signalVSAvoidpower consumption of local amplifier circuit
Core Design Contradiction:
Loss of timeVSUse of energy by moving object

Solution Approach 1:

The precharge circuit charges the local data lines to a high level before the read operation. This preliminary preparation eliminates the need for unnecessary discharge operations that would consume power, allowing early provision of the read enable signal without wasted energy expenditure

Inventive Principle:
Principle #10Preliminary action

3Loss of time

If the read enable signal is provided early, then the time interval is shortened, but both local data lines are discharged simultaneously causing readout errors

Engineering Contradiction:
Improvetime interval between column selection signal and read enable signalVSAvoidreadout error
Core Design Contradiction:
Loss of timeVSObject-generated harmful factors

Solution Approach 1:

The local data lines are precharged to a high level before the read operation. This preliminary action ensures that even if the read enable signal is provided early, the lines are already in the correct state and will not be incorrectly discharged, preventing readout errors while allowing time interval optimization

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11984154B2Local amplifier circuit, data readout method, and memory
Publication Date: 2024.05.14 CHANGXIN MEMORY TECH INC
  • US11984154B2 patent drawing
  • US11984154B2 patent drawing
  • US11984154B2 patent drawing

AI summary

A local amplifier circuit includes write control transistors, configured to connect, based on write enable signal, global data line to local data line; column selection transistors, configured to connect, based on column selection signal, bit line to local data line; first control PMOS transistor having gate connected to local data line, one of source or drain connected to global data line, and the other one connected to read control transistor; and second control PMOS transistor having gate connected to complementary local data line, one of source or drain connected to complementary global data line, and the other one connected to read control transistor. Read control transistors are configured to pull up or down levels at terminals of first control PMOS transistor and second control PMOS transistor, each of which is source or drain connected to a respective one of read control transistors, to preset level based on read enable signal.