Local Amplifying Circuit for Memory Readout Signal Timing
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Solution Overview
Problem
The existing memory systems face issues with read errors and unnecessary power consumption due to the time interval between the column selection signal and the read enable signal, which affects the performance of the memory during data readout operations.
Innovation Solution
A local amplifying circuit is designed with write control transistors, column selection transistors, NMOS transistors, a precharge module, and read control transistors to shorten the time interval between the column selection signal and the read enable signal, ensuring data is fully transmitted before providing the read enable signal, thereby optimizing memory performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the read enable signal is provided when the data is not fully transmitted to the local data line, then the time interval between column selection signal and read enable signal is shortened, but read errors occur and power consumption increases
Solution Approach 1:
The patent applies preliminary action by precharging the local data line and complementary local data line to a first preset level before the read operation begins. This precharging ensures that when the read enable signal is provided early (shortening the time interval), the lines are already in a known state, preventing read errors even though data transmission is not complete. The precharge operation prepares the circuit in advance to handle the early read enable signal safely.
2Loss of time
If the read enable signal is provided when the data is not fully transmitted to the local data line, then the time interval between column selection signal and read enable signal is shortened, but unnecessary power consumption occurs
Solution Approach 1:
The precharge module performs preliminary action by charging the local data line and complementary local data line to a first preset level before the read operation. This prevents unnecessary power consumption that would occur if the lines were discharged and then recharged during an early read operation. By establishing the correct voltage level in advance, the circuit avoids wasteful energy dissipation from unnecessary discharge-recharge cycles.
Solution Approach 2:
The patent changes the voltage parameter of the local data line and complementary local data line by precharging them to a first preset level that is less than the threshold voltage of the control NMOS transistors. This parameter change ensures that the precharged state does not inadvertently turn on the control transistors while still providing a stable starting condition that prevents power waste during early read operations.
3Device complexity
If the local data line and complementary local data line are both at a high level and discharged simultaneously, then the circuit operation is simplified, but read errors occur
Solution Approach 1:
The precharge module performs preliminary action by setting the local data line and complementary local data line to a first preset level before the read operation begins. This preliminary action ensures that even if both lines are at a high level, they are in a controlled, known state that prevents read errors. The precharge operation establishes proper initial conditions that maintain reliability while allowing simplified circuit operation.
Data Source
AI summary
A local amplifying circuit, a data readout method and a memory are provided. The local amplifying circuit includes: write control transistors, configured to connect a global data line to a local data line based on a write enable signal; column selection transistors, configured to connect a bit line to the local data line based on a column selection signal; a first control NMOS transistor, having a gate connected to the local data line, one of a source and a drain being connected to the global data line and the other being connected to a corresponding read control transistor; a second control NMOS transistor, having a gate connected to a complementary local data line, one of a source and a drain being connected to a complementary global data line and the other being connected to a corresponding read control transistor.