Fly Shared Bit Line 4CPP SRAM Cell Architecture

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Solution Overview

Problem

Existing SRAM devices face challenges in independently controlling memory cell rows due to shared source/drain contact structures, leading to coupling issues and limitations in altering supply voltage, and suffer from bit line coupling and loading that degrade read speed.

Innovation Solution

A memory device configured in a 4CPP architecture with double interleaved word lines and fly shared bit lines, reducing bit line length and loading, allowing for independent control of memory cell rows and avoiding bit line coupling.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If shared source/drain contact structures are used in SRAM devices, then device complexity is reduced, but independent control of memory cell rows is lost and coupling issues occur

Engineering Contradiction:

Improvecontact structure complexityVSAvoidindependent row control

Core Design Contradiction:

Device complexityVSEase of operation

Solution Approach 1:

The shared source/drain contact structure is segmented into separate contact structures for different rows. Each row has its own dedicated source/drain contacts, allowing independent control. This segmentation eliminates the coupling issue while maintaining reasonable device complexity through systematic contact allocation.

Inventive Principle:

Principle #1Segmentation

2Device complexity

If conventional bit line structures are used, then device complexity is maintained at acceptable levels, but bit line coupling and loading degrade read speed

Engineering Contradiction:

Improvebit line structure complexityVSAvoidread speed

Core Design Contradiction:

Device complexityVSSpeed

Solution Approach 1:

The bit line structure is segmented into multiple separate bit lines, each serving specific rows. This segmentation reduces the capacitance loading on each bit line and eliminates coupling between adjacent bit lines, thereby improving read speed while keeping the overall structure manageable.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The bit line arrangement is optimized by utilizing vertical stacking and three-dimensional interconnect architecture. Bit lines are routed through multiple layers, effectively increasing the spatial separation and reducing parasitic coupling between bit lines, which improves signal integrity and read speed.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS20240404588A1Fly shared bit line on 4-CPP static random access memory (SRAM) cell and array

Publication Date: 2024.12.05 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A semiconductor device includes a first memory cell, a second memory cell, a third memory cell, and a fourth memory cell operatively arranged along a first one of a plurality of columns, and operatively arranged in a first one, a second one, a third one, and a fourth one of a plurality of rows, respectively. The first column operatively corresponds to a first pair of bit lines and a second pair of bit lines. The first to fourth rows operatively correspond to a first word line, a second word line, a third word line, and a fourth word line, respectively. The first pair of bit lines are operatively coupled to the first and second memory cells. The second pair of bit lines are operatively coupled to the third and fourth memory cells.