Memory Controller Command Address Signal Training
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Solution Overview
Problem
High-speed data accessing systems face challenges in signal training due to significant timing skew between signals, especially at higher speeds like those in DDR4 standards, which complicates the determination of appropriate timing delays for DLL circuits and increases product cost with additional pins for parity checks.
Innovation Solution
A memory controller apparatus with a delay circuit that delays command and address signals using a first delay signal, allowing for command and address training by providing activation signals with first timing and other signals with relaxed second timing, determining the timing 'eye' by varying the delay signal and measuring data feedback, thereby reducing the need for extra pins and improving signal alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If DDR4 standard features including parity checks on command and address signals are implemented, then signal training reliability is improved, but device complexity and product cost increase due to requiring two extra pins
Solution Approach 1:
The patent extracts the parity check function from the physical pin level and implements it through signal processing techniques. The memory controller performs parity checks on command and address signals internally without requiring additional physical pins, thereby maintaining reliability while reducing device complexity
Solution Approach 2:
The patent replaces the mechanical/electrical approach of adding physical pins with a signal processing approach. Instead of using extra hardware pins for parity checks, the system uses software/firmware-based parity verification algorithms that process signals through the existing pin infrastructure
2Manufacturing precision
If training programs execute algorithms to determine timing delays for each memory interface signal, then manufacturing precision is improved, but loss of time increases due to the training process duration
Solution Approach 1:
The patent performs preliminary actions by pre-calculating and storing timing delay values in lookup tables during system initialization. The training program uses these pre-computed values to quickly configure DLL circuits without executing complex algorithms during actual system operation, thereby achieving precise timing while minimizing training time
Solution Approach 2:
The patent creates copies of timing delay parameters in multiple formats (lookup tables, register configurations) that can be quickly applied during system operation. This allows the system to replicate precise timing settings without re-executing the full training algorithm, reducing the time required to achieve manufacturing precision
3Reliability
If delay-locked loop circuits are used to delay DQS signals for correct data latching, then reliability is improved, but device complexity increases due to the need for precise delay adjustment
Solution Approach 1:
The patent implements dynamic adjustability in the delay-locked loop circuits through programmable delay elements that can be configured based on training program results. The system dynamically selects delay values from lookup tables corresponding to different operating conditions, allowing reliable data latching across varying scenarios without requiring overly complex fixed-delay circuits
Solution Approach 2:
The patent changes the delay parameter values in the DLL circuits based on training program output. Instead of using fixed complex delay circuits, the system adjusts delay parameters (delay values stored in registers or lookup tables) to match actual signal propagation characteristics, achieving reliable data latching with simpler circuit architecture
Data Source
AI summary
In one form, an apparatus comprises a delay circuit and a controller. The delay circuit delays a plurality of command and address signals according to a first delay signal and provides a delayed command and address signal to memory interface. The controller performs command and address training in which the controller provides an activation signal and a predetermined address signal with first timing according to the first delay signal, and the plurality of command and address signals besides the predetermined address signal with second timing according to the first delay signal, wherein the second timing is relaxed with respect to the first timing. The controller determines an eye of timing for the predetermined address signal by repetitively providing a predetermined command on the command and address signals, varying the first delay signal, and measuring a data signal received from the memory interface.