Edge Memory Array Mats With Sense Amplifiers and Digit Line Jumpers

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Solution Overview

Problem

Current dynamic random-access memory (DRAM) device arrays have unused memory cells at the edges due to interleaved row segments, where only half of the memory cells are utilized, leading to inefficient use of memory space.

Innovation Solution

The edge memory array is configured to use all memory cells by splitting digit lines and forming sense amplifiers in the gap between them, with digit line jumpers connecting half pairs to form extended lines that can be accessed by sense amplifiers, allowing full utilization of memory cells.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If interleaved row segments are used in edge memory arrays, then sense amplifiers can share reference row segments, but border row segments cannot be used for data storage leading to wasted memory space

Engineering Contradiction:
Improvesense amplifier configurationVSAvoidusable memory cells
Core Design Contradiction:
Ease of manufactureVSQuantity of substance

Solution Approach 1:

The digit lines are segmented into first and second halves, with sense amplifiers positioned at different locations to serve different segments. This segmentation allows border row segments to be independently utilized for data storage while maintaining the interleaved structure for sense amplifier sharing.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a spatial dimension change by positioning sense amplifiers at both ends of digit lines and creating digit line jumpers that extend the effective length. This dimensional approach allows border row segments that were previously unusable to now participate in data storage operations.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Stability of the object's composition

If border row segments are included in interleaved structure, then array continuity is maintained, but only half of the memory cells in border segments are usable

Engineering Contradiction:
Improvearray structure continuityVSAvoidmemory cell utilization
Core Design Contradiction:
Stability of the object's compositionVSProductivity

Solution Approach 1:

The digit line jumpers enable border row segments to serve dual functions: maintaining array continuity in the interleaved structure and simultaneously providing usable data storage capacity. The same physical structure serves both structural and functional purposes.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

Digit line jumpers act as intermediary structures that connect the first and second halves of digit lines across the sense amplifier region. This intermediary connection enables border row segments to be accessed and utilized while preserving the overall interleaved array architecture.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Quantity of substance

If digit lines are split and sense amplifiers are formed in the gap, then all memory cells can be utilized, but device complexity increases

Engineering Contradiction:
Improveusable memory cellsVSAvoiddigit line and sense amplifier configuration
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent merges the first and second halves of digit lines using digit line jumpers to form extended digit lines. This combining approach simplifies the overall structure by creating continuous logical paths while physically utilizing the split configuration to enable full memory cell access.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The digit line configuration is made dynamic through the use of jumpers that can connect different segments based on operational needs. This dynamic reconfiguration allows the system to adapt the digit line paths to utilize all memory cells while managing complexity through flexible connectivity.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS11783887B2Edge memory array mats with sense amplifiers
Publication Date: 2023.10.10 MICRON TECHNOLOGY INC
  • US11783887B2 patent drawing
  • US11783887B2 patent drawing
  • US11783887B2 patent drawing

AI summary

An edge memory array mat with access lines that are split in half, and a bank of sense amplifiers formed in a region that separates the access line segment halves extending perpendicular to the access line segments. The sense amplifiers of the bank of sense amplifiers are coupled to opposing ends of a first subset of the half access lines pairs. The edge memory array mat further includes digit line (DL) jumpers or another structure configured to connect a second subset of the half access line pairs across the region occupied by the bank of sense amplifiers to form combined or extended access lines that extend to a bank of sense amplifiers coupled between the edge memory array mat and an inner memory array mat.