ST-MRAM Write Driver Circuit for Leakage Reduction
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Solution Overview
Problem
Spin-torque MRAM experiences high leakage current and power supply noise immunity issues during writing operations, limiting its scalability and reliability due to high switching currents and voltage drops across long bit and source lines.
Innovation Solution
A write driver circuit utilizing NMOS-follower and PMOS-follower circuits to apply voltages at both ends of bit and source lines, minimizing voltage drop and sub-threshold leakage, thereby reducing effective metal resistance and enhancing power supply noise immunity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single current pulse is applied to write to spin-torque MRAM, then the write operation can be completed, but sub-threshold leakage current increases and power consumption rises
Solution Approach 1:
The write driver is segmented into multiple independent voltage sources (first voltage source, second voltage source, third voltage source, fourth voltage source) that can be independently controlled. This segmentation allows selective activation of voltage sources based on write requirements, enabling the system to reduce leakage current by keeping voltage sources in high-impedance state when not actively writing, while still achieving fast write operations when needed.
2Reliability
If high switching currents are used to ensure reliable writing, then write error rate decreases, but voltage drops across bit and source lines increase
Solution Approach 1:
The patent introduces a fourth voltage source connected to the opposite end of the source line from the third voltage source, and similarly positions voltage sources at both ends of bit lines. This spatial distribution across multiple dimensions of the circuit allows the system to overcome voltage drops by providing voltage support from multiple locations simultaneously, ensuring reliable writing even across long bit and source lines with high resistance.
Solution Approach 2:
Multiple voltage sources act as intermediaries to compensate for voltage drops in the bit and source lines. By positioning voltage sources at strategic locations along the lines, the system mediates the voltage distribution to ensure sufficient voltage reaches the memory cell during write operations, thereby reducing write error rates without requiring excessively high current from a single source.
3Speed
If voltage sources are continuously active to maintain readiness, then write speed is maintained, but power consumption increases
Solution Approach 1:
The voltage sources are designed to be dynamically controllable, transitioning between active voltage output mode and high-impedance mode. This dynamic behavior allows the system to maintain fast write speed when writing is required while minimizing power consumption during idle periods, as voltage sources can be switched to high-impedance state when not actively driving write operations.
Solution Approach 2:
The voltage sources operate in periodic cycles, being activated only during write operations and remaining in high-impedance state during non-write periods. This periodic activation pattern ensures that the system maintains readiness for fast write operations while minimizing continuous power consumption, as each voltage source is only actively supplying voltage when a write operation is actually occurring.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively minimizes sub-threshold leakage and reduces effective metal resistance, improving power supply noise immunity and enabling more efficient writing operations in spin-torque MRAM, thus enhancing its scalability and reliability.
Implementation Method 1
The angular momentum carried by the spin-polarized tunneling current causes reversal of the free layer
Implementation Method 2
exhibits an electrical resistance that depends on the magnetic state of the device
Data Source
Figure 1
Figure 2
Figure 3~4
AI summary
A write driver for writing to a spin-torque magnetoresistive random access memory (ST-MRAM) minimizes sub-threshold leakage of the unselected (off) word line select transistors in the selected column. An effective metal resistance in the bit line and/or source line is reduced and power supply noise immunity is increased. Write driver bias signals are isolated from global bias signals, and a first voltage is applied at one end of a bit line using one of a first NMOS-follower circuit or a first PMOS-follower circuit. A second voltage is applied at opposite ends of a source line using, respectively, second and third PMOS-follower circuits, or second and third NMOS-follower circuits.