Memory Integrated Circuit Addressing Method
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Solution Overview
Problem
Conventional serial flash memory is limited to 128 megabits due to the 24-bit address constraint, restricting its storage capacity and potential applications, and modifying memory devices to expand capacity often breaks compatibility with existing standards, making it difficult to expand memory without affecting existing users.
Innovation Solution
Implementing a new interface for integrated circuit memory that allows access to memory spaces greater than 128 megabits by using separate command codes for high and low order address bits, enabling compatibility with existing serial flash specifications and expanding addressable memory without altering existing instruction sets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a 24-bit address stream is used for serial flash memory, then compatibility with existing SPI standards is maintained, but the addressable memory space is limited to 128 megabits
Solution Approach 1:
The patent segments the 32-bit address into two parts: a 24-bit lower address portion transmitted through the existing SPI interface, and an 8-bit upper address portion stored in a dedicated register. This segmentation allows the system to maintain compatibility with 24-bit address SPI standards while enabling access to larger 32-bit address spaces beyond 128 megabits.
Solution Approach 2:
The patent embeds the upper 8 bits of the address within the memory controller's register structure, nesting the extended address information inside the existing SPI flash interface framework. This allows the extended addressing capability to be integrated without requiring changes to the external SPI protocol or existing user interfaces.
2Quantity of substance
If the address bits are increased beyond 24 bits to expand memory capacity, then the addressable memory space increases, but compatibility with existing SPI standards and instruction sets is broken
Solution Approach 1:
The patent divides the address transmission into two segments: the lower 24 bits are transmitted through the standard SPI interface maintaining protocol compatibility, while the upper 8 bits are handled through a separate register mechanism. This segmentation resolves the contradiction by allowing extended addressing without breaking existing SPI standard compliance.
Solution Approach 2:
The patent introduces a register as an intermediary between the SPI interface and the memory array. This register holds the upper address bits and mediates between the standard 24-bit SPI addressing and the extended 32-bit address space, allowing both compatibility and expansion to coexist.
3Quantity of substance
If existing memory devices are modified to expand addressable range, then memory capacity is increased, but difficulty is added for existing users familiar with common standards
Solution Approach 1:
The patent segments address handling into automatic and manual portions: the lower 24 bits continue to work automatically through the standard SPI interface as before, while the upper 8 bits are optionally configured through registers. This maintains ease of use for existing applications while enabling expanded capacity when needed.
Solution Approach 2:
The patent performs preliminary configuration of the upper address bits in registers before SPI flash operations. This preliminary action allows the extended addressing to be set up once, after which standard SPI operations continue to work unchanged, maintaining ease of operation for existing users.
Data Source
AI summary
A memory integrated circuit has control circuitry that accesses memory cells of the memory integrated circuit. The control circuitry is responsive to commands including a first command and a second command. The first command specifies a high order set of address bits. The second command specifies a low order set of address bits. The high order set of address bits and the low order set of address bits constitute a complete access address of the memory integrated circuit. The first command and the second command have different in command codes.


