Multi-tier Memory Voltage Regulation for 3D Stacked Dies
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Solution Overview
Problem
Conventional circuit designs face challenges in managing process skew and temperature variations between stacked dies in 3D chip configurations, leading to inefficiencies and increased costs due to the need for expensive binning and guard bands, which are not feasible for wafer-to-wafer bonding.
Innovation Solution
Implementing localized voltage regulators per layer with a small voltage offset (ΔV) to balance process and temperature variations between layers, using a Z-dimension power grid to distribute voltage uniformly across multiple layers, and allowing independent power management of each layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional circuit designs use stacked dies in a layered chip, then integration density is improved, but process skew and temperature variations between layers increase
Solution Approach 1:
The patent divides the power delivery system into multiple independent voltage regulator modules, each serving a specific layer. This segmentation allows each layer to have its own voltage regulation, compensating for process skew independently and improving reliability while maintaining high integration density.
Solution Approach 2:
The patent implements layer-specific voltage offset adjustments, where each voltage regulator module can apply different voltage offsets to different layers based on their specific process and temperature conditions. This local quality approach directly addresses process skew variations between layers.
2Manufacturing precision
If binning based on testing process corners is used to remove process skew, then process matching is improved, but manufacturing cost increases
Solution Approach 1:
The patent uses voltage offset parameters to compensate for process variations instead of physical binning. By adjusting voltage parameters dynamically, the system achieves process matching without the need for expensive testing and sorting procedures, reducing manufacturing cost while maintaining precision.
3Productivity
If wafer-to-wafer bonding is used for stacking, then integration density is improved, but binning becomes infeasible
Solution Approach 1:
The patent segments the voltage regulation function into distributed modules across different layers, enabling post-bonding calibration. This segmentation makes the system adaptable to wafer-to-wafer bonding by allowing individual layer adjustments after stacking, making binning infeasible while maintaining integration density.
Solution Approach 2:
The patent implements dynamic voltage offset adjustment capability that allows calibration after bonding. This dynamic adaptation enables the system to compensate for process variations even when binning is not performed, making wafer-to-wafer bonding feasible without sacrificing manufacturing quality.
4Reliability
If guard bands are used to manage process skew, then reliability is improved, but performance is reduced
Solution Approach 1:
The patent applies local voltage compensation to specific layers experiencing process skew, rather than using global guard bands. This localized approach maintains reliability by addressing only the affected layers, preserving overall system performance without unnecessary conservatism.
Solution Approach 2:
The patent uses voltage parameter adjustments to compensate for process skew instead of relying on guard bands. By changing voltage parameters dynamically, the system achieves reliable operation at higher performance levels without the performance penalty associated with conservative guard band design.
Data Source
AI summary
Various implementations described herein are related to a device having voltage regulation architecture with multiple layers arranged in a multi-layer structure. The device may include one or more layers of the multiple layers with voltage regulation circuitry that may be configured to manage at least one of process variation and temperature variation between the multiple layers of the multi-layer structure.