VSS-Sensing Amplifier Leakage Reduction via Half-Voltage Precharge
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional VSS-sensing amplifiers in embedded Dynamic Random Access Memory (eDRAM) experience high leakage current when bit lines are pre-charged to ground reference voltage VSS, leading to reduced data retention performance and increased power consumption during long retention periods.
Innovation Solution
The bit lines are pre-charged to half of the supply voltage (½ VDD) during the retention mode, reducing leakage current by using a specific voltage level (VREST) that minimizes current leakage from memory cells, thereby improving retention performance and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bit lines are pre-charged to ground reference voltage VSS, then the sensing amplifier can operate in conventional VSS-sensing mode, but leakage current from memory cells to bit lines increases significantly
Solution Approach 1:
The patent changes the voltage parameter of bit lines from conventional VSS (ground) to VREST (retention voltage approximately equal to VDD/2). This parameter change reduces the voltage differential between memory cell storage nodes and bit lines, thereby minimizing leakage current while maintaining data retention capability during standby mode.
Solution Approach 2:
The patent applies preliminary action by pre-charging bit lines to VREST before entering retention mode. This preliminary voltage setting prepares the bit lines to minimize leakage current from the outset during the retention period, rather than using the conventional VSS precharge that causes high leakage.
2Ease of operation
If bit lines are pre-charged to ground reference voltage VSS, then the sensing amplifier operates conventionally, but power consumption increases during long retention periods
Solution Approach 1:
The patent modifies the operating parameter of bit lines by setting them to VREST instead of VSS during retention mode. This parameter modification reduces the electric field driving leakage current, thereby lowering power consumption while the sensing amplifier remains operational and ready for rapid activation when needed.
Solution Approach 2:
The patent introduces dynamic operation by switching bit line voltage between VSS (during active read/write operations) and VREST (during retention mode). This dynamic voltage adjustment optimizes power consumption during stationary retention periods while maintaining the ability to quickly transition to operational mode when data access is required.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
Some embodiments regard a circuit comprising a memory cell (MC), a first data line (BL), a second data line (BLB), a sensing circuit (SENPAIR) coupled to the first data line (BL) and the second data line (BLB), a node (NVR) selectively coupled to at least three voltage sources via at least three respective switches (N7-N9), a fourth switch (N2), and a fifth switch (N3). A first voltage source is configured to supply a retention voltage (VREST) to the node (NVR) via a first switch (N9). A second voltage source is configured to supply a ground reference voltage (VSS) to the node (NVR) via a second switch (N8), and a third voltage source is configured to supply a reference voltage (VREF) to the node (NVR) via a third switch (N7). The fourth switch (N2) and fifth switch (N3) are configured to receive a respective first control signal (RWL) and second control signal (ZRWL) and to pass a voltage at the node (NVR) to the respective first data line (BL) and second data line (BLB).