3D Memory Array Structure Vertical Stacking Reduces Manufacturing Cost
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Solution Overview
Problem
Conventional three-dimensional (3D) array structures for memory devices are expensive and time-consuming to manufacture due to the advanced lithography processes involved, limiting the cost-effectiveness of high-density memory device production.
Innovation Solution
A novel 3D array structure is developed with transistors arranged in a common column and base structure configuration, allowing for efficient use of space and reduced manufacturing complexity, featuring semiconductive layers with impurity-doped regions and connector structures connected to memory layers, enabling the formation of bipolar junction transistors for high-density memory devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional layer-by-layer stacking process is used to manufacture 3D array structures, then high memory density is achieved, but manufacturing cost and time increase significantly
Solution Approach 1:
The patent transitions from conventional planar 2D array structures to a true 3D architecture where transistor arrays are stacked vertically above memory layers. Multiple transistor arrays (first and second transistor arrays) are positioned at different vertical levels, each addressing different surface portions (first and second surface portions) of the memory layer. This vertical stacking enables high memory density by utilizing the third dimension (height) rather than only expanding horizontally, while the shared common electrode and interconnected structures reduce the number of separate manufacturing cycles needed compared to traditional layer-by-layer stacking.
2Quantity of substance
If advanced lithography processes are used to manufacture conventional 3D array structures, then high memory density is achieved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent merges multiple transistor arrays with a shared memory layer through common electrodes and interconnected structures. The first and second transistor arrays both connect to the same memory layer via a common electrode, allowing multiple transistor arrays to be integrated without requiring separate, complex lithography processes for each layer. The common column structures and shared base structures further consolidate the architecture, reducing manufacturing steps while achieving high density through vertical integration rather than through complex planar patterning.
3Quantity of substance
If more transistor arrays are added to increase memory capacity, then memory density improves, but manufacturing time and cost increase
Solution Approach 1:
The patent enables continuous integration of multiple transistor arrays by establishing interconnected structures that link the first and second transistor arrays through common electrodes and shared base structures. This continuous architecture allows memory capacity to be expanded by adding transistor arrays at different vertical levels without requiring discrete, time-consuming manufacturing cycles for each addition. The interconnected design permits parallel processing and reduces idle time between manufacturing steps, as structures can be formed and connected in an integrated sequence rather than through repeated sequential layer stacking.
Data Source
AI summary
A disclosed memory device includes a three-dimension array structure that includes memory layers and transistor structures disposed between the memory layers. Each memory layer is connected to a common electrode, and each transistor structure includes transistors that share common column structures and common base structures. The transistors also each include a connector structure that is spaced apart from a common column structure by a common base structure.