3D Nonvolatile Memory Asymmetric Slimming Region Design
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Solution Overview
Problem
In 3D nonvolatile semiconductor devices, the formation of slimming regions on both sides of word lines and pass transistors in cell regions increases the area, limiting integration density and process margins due to the need for multiple wells for pass transistors.
Innovation Solution
A 3D nonvolatile memory device design where the slimming region is formed only on one side of the word line stack, with a larger width than the cell region, allowing for a stepped pattern that reduces overall area and ensures process margins by optimizing the arrangement of pass transistors and word lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If slimming regions are formed on both sides of word lines and pass transistors are arranged in both sides of cell regions, then process margins are ensured, but device area increases
Solution Approach 1:
The patent applies asymmetry by forming slimming regions only on one side of the word line stack rather than symmetrically on both sides. This asymmetric configuration reduces the total device area while maintaining sufficient process margins through optimized spatial arrangement of the slimming region adjacent to the cell region
Solution Approach 2:
The patent utilizes vertical stacking in the third dimension to arrange multiple word line stacks and their associated slimming regions. By stacking structures vertically rather than expanding horizontally, the design achieves high integration density while maintaining adequate slimming region dimensions for process margins
2Reliability
If multiple wells for pass transistors are formed, then transistor functionality is ensured, but slimming region area increases
Solution Approach 1:
The patent merges the slimming region with the cell region structure, where the slimming region is formed adjacent to and integrated with the cell region rather than as a separate entity. This integration allows pass transistors to be efficiently arranged while minimizing the total area occupied by slimming regions
Solution Approach 2:
Multiple pass transistors are arranged in the vertical dimension through stacking, allowing multiple wells to be formed without proportionally increasing the planar area of slimming regions. The vertical stacking enables high-density integration while maintaining sufficient space for all necessary transistor wells
Data Source
AI summary
A 3D nonvolatile memory device is disclosed. The 3D nonvolatile memory device includes a word line stack in which a plurality of word lines are stacked therein and includes a cell region and a slimming region, and pass transistors located below the word line stack, and electrically coupled to the slimming region. A width of the slimming region is larger than that of the cell region.