3D Semiconductor Memory Device With Auxiliary Gate Insulating Patterns
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Solution Overview
Problem
Conventional 2D semiconductor memory devices face limitations in increasing integration level and cost-effectiveness, with 3D devices requiring advanced technologies for reliable mass production.
Innovation Solution
A three-dimensional semiconductor memory device design featuring a vertical channel structure with interlayer insulating layers, gate electrodes, and auxiliary gate insulating patterns, including materials like tungsten, titanium, and aluminum nitride, to enhance reliability and reduce costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional 2D memory device structure is used, then manufacturing process is simpler, but integration level is limited
Solution Approach 1:
The patent transitions from conventional 2D memory structure to a 3D vertical channel structure extending in the vertical direction. This dimensional change allows multiple gate electrodes to be stacked vertically around the channel, significantly increasing the integration level without requiring more complex planar patterning processes.
Solution Approach 2:
The patent implements a nested structure where multiple gate electrodes are arranged concentrically around the vertical channel structure at different heights. The gate electrodes surround the channel in a nested configuration, maximizing space utilization and achieving high integration within a compact footprint.
2Manufacturing precision
If 3D memory device structure is implemented, then integration level increases, but manufacturing reliability decreases
Solution Approach 1:
The patent introduces auxiliary gate insulating patterns between the gate electrodes and the vertical channel structure to prevent harmful effects. These auxiliary patterns act as protective barriers that cushion against potential manufacturing defects or electrical breakdown, thereby improving product reliability while maintaining the 3D structure.
Solution Approach 2:
The auxiliary gate insulating patterns serve as intermediary layers between the gate electrodes and the channel structure. These intermediaries provide electrical isolation and structural buffer zones, ensuring reliable operation of the 3D memory device by preventing direct contact and potential failure modes.
3Ease of manufacture
If conventional micro patterning technology is used, then manufacturing cost is high, but integration level is limited
Solution Approach 1:
By moving to a vertical 3D architecture, the patent achieves high integration without relying on advanced planar micro patterning. The vertical stacking of gate electrodes around the channel allows conventional patterning techniques to be used effectively, reducing equipment costs while maintaining high density.
Solution Approach 2:
The vertical channel structure with surrounding gate electrodes serves multiple functions: it provides high integration density, enables conventional manufacturing processes, and maintains electrical performance. This multi-functional design makes the structure universally applicable and cost-effective for mass production.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design improves the integration level and reliability of semiconductor memory devices while reducing production costs, with the auxiliary gate insulating patterns effectively suppressing charge migration and enhancing data retention.
Implementation Method 1
the auxiliary gate insulating patterns are disposed between the gate electrodes and the vertical channel structure and include a material having fixed charges
Data Source
AI summary
A three dimensional semiconductor memory device includes a vertical channel structure extending in a vertical direction on a substrate; interlayer insulating layers surrounding the vertical channel structure and being stacked in the vertical direction on the substrate, gate electrodes surrounding the vertical channel structure and being disposed between the interlayer insulating layers, corners of the gate electrodes adjacent to the vertical channel structure being rounded, and auxiliary gate insulating patterns disposed between the gate electrodes and the vertical channel structure, wherein a side surface of the auxiliary gate insulating pattern is substantially coplanar with a side surface of the interlayer insulating layer in the vertical direction on the substrate.