3D Memory Back-Gate Adjacent Cell Operation Control
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Solution Overview
Problem
Current three-dimensional (3D) memory devices face challenges in optimizing operations for memory cells adjacent to back-gate transistors, as conventional operations do not account for distinct core operation conditions or policies, leading to suboptimal performance compared to normal cells.
Innovation Solution
The implementation of a 3D memory device with a pipe-shaped bit cost scalable (PBiCS) structure, including memory blocks with pillar-shaped semiconductor layers and a back-gate transistor, and a memory controller that differentiates operations for adjacent cells by varying core operation conditions or policies, such as program and read parameters, to enhance performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional 3D memory devices use uniform operations for all memory cells, then device complexity is reduced, but programming, reading, and erasing performance deteriorates due to inability to handle adjacent cell differences
Solution Approach 1:
The patent applies local quality by differentiating operations between memory cells adjacent to the back-gate transistor and non-adjacent cells. The control logic identifies adjacent cells through address decoding and applies specialized programming, reading, and erasing sequences tailored to their unique electrical characteristics, while non-adjacent cells receive standard operations. This localized differentiation resolves the contradiction by improving reliability for critical cells without unnecessarily complicating the entire device operation.
Solution Approach 2:
The control logic dynamically adjusts operation parameters based on cell location. The system determines whether a cell is adjacent to the back-gate transistor during address decoding and automatically selects appropriate operation sequences. This dynamic adaptation allows the device to optimize performance for different cell types without requiring separate hardwired circuits for each cell type, thus improving reliability while managing complexity through software-based control.
2Measurement precision
If differentiated operations are implemented for adjacent cells, then programming, reading, and erasing accuracy improves, but device complexity increases due to additional control logic
Solution Approach 1:
The control logic unit performs multiple functions: it decodes addresses to identify cell locations, determines adjacency to the back-gate transistor, and selects appropriate operation sequences. By consolidating these functions into a single multi-functional control logic unit, the patent achieves differentiated operations for improved accuracy while minimizing the increase in device complexity compared to having separate dedicated circuits for each function.
3Reliability
If adjacent cell operations are optimized with different voltage and timing parameters, then operation reliability improves, but manufacturing and control difficulty increases
Solution Approach 1:
The control logic pre-establishes different operation sequences and voltage/timing parameters for adjacent versus non-adjacent cells during device initialization or configuration. These predetermined parameter sets are stored in the control logic, allowing the system to automatically apply appropriate parameters without real-time complex calculations. This preliminary preparation improves operation reliability through optimized parameters while simplifying control management by using pre-defined rather than dynamically calculated settings.
Data Source
AI summary
A storage device is provided. The storage device includes a memory controller and at least one nonvolatile memory device including memory blocks having a pipe-shaped bit cost scalable (PBiCS) structure. Each of the memory blocks penetrates word lines stacked on a substrate in the form of plates and includes a first pillar, a second pillar, and a back-gate. The second pillar includes a semiconductor layer, an insulating layer, and a charge storage layer. The back-gate includes a pillar connection portion to connect the first and second pillars to each other and is disposed between the substrate and the word lines. The memory controller includes an adjacent cell management unit configured to control the at least one nonvolatile memory device such that a program operation, an erase operation or a read operation is performed on memory cells adjacent to the back-gate, unlike the other memory cells.