Solid-State Devices TRIZ Cases

A vertical TFT structure around a penetrating opening packs more transistors into the array substrate while preserving pixel aperture for higher display resolution.

Segmented deep isolation and extended active regions cut pixel cross-talk while preserving gate size in dense CMOS image sensors.

Symmetric main and backup pad placement keeps repaired micro-LED sub-pixels aligned, preserving light output consistency and display uniformity.

Overlapping contact holes and a dam improve thin-film uniformity and match reflectance across tiled display module seams.

A curved anisotropic conductive layer improves micro-LED bonding strength and fixation while reducing ESD during display assembly.

Pneumatic pressure and adhesive protrusions improve micro LED transfer accuracy on larger substrates, cutting arrangement errors and transfer time.

A tuned green spectrum balances Rec. 2020 color gamut with M-cone stimulation by controlling peak ratios and spectral distribution.

Pixel separation walls and diffusion regions improve phase difference detection while limiting image information loss in autofocus imaging.

Dam wall units between COB LED elements interrupt total internal reflection under the cover layer, increasing output light and display brightness.

Selective etching forms a stilted backside pad that enlarges bond area, improves BSI bondability, and lowers delamination risk.

Metal boundary trenches and oxide pixel trenches cut lateral photon crosstalk while preserving quantum efficiency in CMOS image sensors.

A resin layer joined to a PCB avoids back-side glass wiring, cuts PCB layers, and reduces breakage in LED display module manufacturing.

Hinged pixels and multiple bias-generating pixels cut bias noise, ease glass-substrate manufacturing, and improve sensor isolation.

A back-side deep trench with a doped liner improves pixel isolation, reducing crosstalk and blooming while preserving photodiode area.

Refractive-index layer stacking reflects unconverted blue light back into the color converter, improving display light output efficiency.

A removable protection layer shields the micro lens during planarization, preventing damage and contamination before fiber attachment.

Vertical stacking of micro LEDs and driving chips cuts package size and light loss while enabling active matrix display pixels.

A shielded dual-signal-line pixel layout enables simultaneous adjacent-row readout, preserving frame rate and reducing cross-talk.

An insulating via layout blocks direct ENIG contact with the base, preventing abnormal metal growth while preserving flatness and bond reliability.

Separating the driver chip and micro LED emitters into stacked layers shrinks package area, cuts light loss, and supports higher pixel density.

Lens arrays with high-absorption layers and deep trench isolation boost low-light photodiode efficiency while limiting cross-talk.

Segmented sub-pads replace separate LED wiring, enabling compact series or parallel layouts with lower heat and better reliability.

Nanorod subpixels and a red color conversion layer improve micro LED color resolution, light efficiency, and manufacturability.

Stacked 2D power wiring across APD pixel regions reduces resistance, stabilizes current supply, and supports efficient photon counting at high luminance.

Shared pixel lines and logarithmic conversion improve low-light event detection by expanding dynamic range without sacrificing imaging resolution.

Sequential wet and dry etching clears metal oxides in TFT channel formation, lowering contact resistance and improving display yield.

A vertically stacked micro-LED with color filters increases luminous area for red and green pixels without enlarging pixel footprint.

A stacked transistor-over-emitter layout with a reflective electrode boosts light extraction and reliability in high-resolution display pixels.

A thicker conductive layer replaces fine metal grids in micro LED arrays to improve high-resolution yield, brightness uniformity, and power use.

Grooves in the planarization layer let the PDL cover anode ends, preventing etch exposure, oxidation, short circuits, and uneven brightness.

A same-side wirebondable electrode layout improves SSL die light extraction, current spreading, and manufacturing alignment tolerance.

Ion-implanted isolation replaces mesa etching in micro-LEDs, improving substrate adhesion, limiting sidewall damage, and confining current flow.

A three-stage epitaxial source/drain process adds a shaping section to improve etch selectivity, fin isolation, and doping control at smaller pitches.

Segmented metal portions placed between adjacent data lines raise pixel density and resolution while preserving display aperture.

Specific TADF dopant lifetimes and host energy levels improve triplet use, boosting OLED efficiency and operating life.

Integrated ESD bridges on display connection lines dissipate static charge while shrinking pad-area overhead and protecting pixel circuitry.

Spherical fillers in the optical layer improve light extraction and reduce RGB color differences, helping large display panels maintain image quality.

Glue residue on supporting structures helps retain and align micro-LEDs during transfer, improving placement yield and shortening cycle time.

A 5T SRAM cell uses mid-level bit-line precharge and a reference bit line to shrink cell area while speeding sense amplifier reads.

Through-hole mesa layout and multilayer insulation improve current spreading and block moisture in UV vertical LEDs.

A transparent sidewall-and-ceiling protection film blocks moisture and impurities in image sensors while preserving optics and reducing dark current.

Reflective metal layers and ordered photonic structures steer micro LED light more directionally for efficient AR and VR displays.

Curved substrate surfaces split incident light for phase detection, improving autofocus accuracy and edge-to-edge image sharpness.

Interconnected top and bottom mesa links free panel space, block light cross-talk, and cut power use in dense micro LED arrays.

Wider bank openings improve inkjet placement of color conversion layers in high-resolution displays while reducing light absorption and boosting luminance.

Ramp-based comparator and counter gating cuts ADC power use and noise during CMOS pixel signal conversion.

Adjacent same-function transistors and separated signal paths reduce image quality variation, color mixture, and parasitic capacitance.

An offset light source and added optical element redirect reflected light into shadowed regions, reducing occlusion in compact scanning mirror illumination.

Anisotropic pad sizing and protective openings improve dense Mini LED and Micro LED substrate bonding while limiting oxidation and abnormal growth.

Controlled anti-reflection and metal pattern slopes prevent etching undercut, cut reflection, and improve display substrate yield.

Adjacent columnar-crystal scintillator panels with a continuous adhesive layer expand detection area while preserving image resolution and attachment stability.

Multiple monolithically integrated emission regions enable wide-range dimming while keeping LED chip efficiency and color output stable.

An anti-arcing contact and insulating pattern enable denser 3D memory stacks without the electrical reliability loss and cost of finer patterning.

Bent, widened fan-out wires cut impedance while using redundant edge space to keep the display panel side frame narrow.

Pressure-sensed transfer and substrate tilt adjustment improve LED bonding alignment on large display substrates while reducing defects and cost.

Monolithic pixel resistors limit peak current in GmAPD focal plane arrays, improving optical overstress tolerance without major timing jitter loss.

Segmented diode regions and floating strips shorten diode span to protect MOSFET terminals from ESD while keeping leakage current at nanoAmpere levels.

A side-contact connection layer avoids insulating-layer openings, protects the photoelectric film, and supports stable low-power spectral switching.

Hybrid bonding links a silicon X-ray detector chip to CMOS readout for faster photon counting and energy-resolved mammography with fewer false positives.

A dual hydrogen barrier and high-density dielectric protect ferroelectric trench capacitors from hydrogen during logic integration.

Vertical RGB layer stacking lets micro LED sub-pixels be staggered through transparent regions, reducing placement precision limits and improving yield.

Histogram-based time-to-digital counting improves weak-light ranging precision while reducing memory use and converter hardware cost.

Patterned insulating openings define the LED light-emitting layer without etching, improving small-size process control, yield, and quality.

DC-biased resistivity switching layers let one compact antenna structure transmit in opposite directions without separate antenna assemblies.

A conductive-polymer trench fill reduces mechanical and electrical stress, enabling thinner dielectrics with higher capacitance density and voltage.

Segmented pixel isolation and local separation structures cut crosstalk between photoelectric regions to improve autofocus signal quality.

A boron-carbazole heterocyclic emitter improves OLED efficiency and lifespan by enabling TADF and suppressing triplet-related quenching.

By setting the sensor incident surface near the Brewster angle, this module reduces surface-reflected light interference and improves image quality.

Moving MRAM to backside BEOL frees frontside routing space, cuts resistance and parasitic capacitance, and protects sensitive chip components.

Alternating organic coating and adhesive layers seal rough display panel side surfaces with lower thickness, better stress absorption, and moisture protection.

Thin insulating layers in COP bonding block ACF particle migration between adjacent terminals while preserving vertical electrical conduction.

A vertically positioned PCM heater cuts parasitic resistance and programming current while preserving cell density for analog AI memory.

A multi-level electrode pad with platform and depression areas improves current spreading, light efficiency, and LED reliability in compact displays.

Wider shared inner electrode sections and an etch-stop layer enable denser 3D ferroelectric memory with fewer fabrication defects.

Thinning a foundry wafer and oxide-bonding it to a higher-resistivity substrate cuts parasitic losses and improves isolation and Q factor.

Edge trimming leaves a flange around the bonded wafer so backside grinding thins the center without edge cracking, peeling, or carrier damage.

Via-hole conductive shields block light at the TFT channel while maintaining stable electrode connections for more reliable OLED panels.

A stacked TFT layout uses a shielding conductive layer and flat planarization to preserve pixel aperture while stabilizing second-TFT driving.

A separation zone and inclined side surfaces block boundary light leakage between adjacent modules, preventing bright or dark display lines.

A transfer layer with regular crystal orientation is bonded onto a dielectric surface to improve spectral chip transmittance and modulation efficiency.

A dual-resistivity package structure replaces metal electrodes in micro LED panels, easing precision demands, cutting cost, and improving yield.

A cavity-spaced core-shell LED structure cuts stress defects while a passivation layer and textured surface improve light extraction.

Optical shielding and doped-undoped superlattice layers improve carrier separation for high-gain, fast wide-spectrum photodetection.

Textured photon-mixing structures boost absorption in Geiger-mode diode arrays, improving LIDAR sensitivity, dynamic range, and timing.

A shaped heat-curable resin molding protects LEDs from moisture and static while cutting coating time and solution use.

A relay electrode links capacitor and wiring layers through the insulating film, cutting separate trench and contact steps in display fabrication.

Multi-stage wet and dry etching removes conductive by-products from TFT gate formation, blocking leakage paths and improving display transistor reliability.

Varying groove opening ratios and heat paths in one substrate enables smaller full-color LEDs with tunable wavelengths and better heat transfer.

An opposite-doped RESURF region extends depletion in a MOS varactor, lowering minimum capacitance while preserving Q factor.

Individually controlled pickup elements and adhesive contact enable selective LED placement, improving subpixel accuracy and reducing display defects.

Dielectric anti-diffusion layers in sensor through-passages block metal contamination while preserving pixel isolation and electrical connections.

An angled contact layout across a band-shaped insulator narrows pixel isolation while preserving transfer-gate symmetry and signal transfer efficiency.

Preforming through mold vias in the protective film simplifies PoP packaging, improving alignment accuracy, yield, strength, and warpage control.

A metal-oxide intermediary insulating layer protects downsized light-emitting elements from process damage while preserving luminous efficiency.

A protective layer shields mesa sidewalls and the exposed reflective layer during backside polishing, improving vertical LED reliability and light extraction.

Overlapping nano antenna layers use band-specific resonance to boost light absorption and cut color-band crosstalk in low light.

A heterocycle-amino organic compound boosts blue OLED luminous efficiency by improving conjugation and resonance while extending service life.

An amorphous trench base and laser-annealed monocrystalline islands reduce GaN epitaxial cracking from thermal and lattice mismatch.

Interior mixing chambers in LED support elements extend light paths to improve near-field and far-field uniformity in low-profile packages.

A current blocking layer in the ohmic region limits injection at peak heating zones, improving heat dissipation and LED reliability.

An overlapping second substrate and sidewall case create a sealed display structure that blocks moisture ingress without added thickness.

A spaced ring-frame transfer process replaces wafer adhesive tape without cutting near the wafer, reducing damage and contamination.

Segmented photoelectric regions and deep isolation extensions improve CMOS pixel charge transfer and raise full well capacity without enlarging pixel area.

Configurable source-drain connections tune CMOS delay and output skew while keeping a uniform cell footprint across PVT variation.

Input signal frequency sets IC operating modes through shared terminals, cutting configuration pin count, cost, and circuit complexity.

Program-controlled pin reassignment replaces fixed wire bonding, cutting packaging cost while keeping chip pin functions flexible.

By stopping selected logic blocks based on cumulative run time, this case cuts power use while limiting degradation-driven clock skew.

Passive alignment via embedded lens and registration features eliminates active feedback systems, reducing assembly time and cost.

Subtractive etch creates symmetric MIEC contacts, eliminating CMP defects and reducing leakage current in back-end-of-line memory devices.

Segmented sputtering layers optimize adhesion to insulators while protecting bonding interfaces from oxidation, resolving peeling issues at connection pads.

A non-volatile memory gate structure incorporates a bottom nitride layer to enable charge trapping.

Merging gate electrodes into the data line eliminates contact holes, raising aperture ratio while preventing wire breakage.

A display device uses a temperature-dependent reflection-reducing layer to manage light reflectance.

A nitride semiconductor light emitting device uses a silicon substrate with a super-lattice buffer layer to enhance electrical and optical characteristics.

A flexible display drive controller adjusts its aspect ratio to fit within the bend area of a flexible substrate.

A flexible electronic device package uses a clad barrier film to protect internal components from environmental damage.

Tensile silicon nitride film on n-MOSFETs increases electron mobility, reducing insertion loss while maintaining withstand voltage.

Hydrophilic particles self-align on insulation layers to expose conductive lines for variable resistance element formation.

A display substrate connection terminal uses stacked conductive layers to maintain electrical continuity during manufacturing.

A light emitting particle-polymer composite uses thiol and unsaturated monomers to form a stable matrix.

Four sequential light-emitting units expand the color gamut and improve saturation to resolve limited color reproducibility in traditional displays.

A semiconductor memory device integrates a resistive body in the peripheral area using shared insulating layers to optimize chip surface utilization.

Alternating dual metal layer bit lines with grounding shields reduce parasitic capacitance, eliminating sequential sensing delays and improving read accuracy.

Segmented 3D memory blocks enable independent voltage application to word lines for arbitrary cell reading.

A driver circuit monitors IGBT state variables using two parameters set by single pins to enable flexible two-stage switching.

An ion blocking layer shields the active layer of thin-film transistors during manufacturing.

A segmented adhesive layer structure enables precise positioning and stable attachment of miniature semiconductor elements during transfer processes.

Differentiated control logic optimizes program and read accuracy for back-gate adjacent cells without increasing device complexity.

Angled spacer placement in display substrates reduces sub-pixel shielding, resolving color shift at oblique viewing angles.

Stacked transparent electrodes increase capacitance while enabling one-drop filling processes.

Asymmetric microLED clusters replace expensive VCSEL arrays to lower manufacturing costs while maintaining precise dot projection for facial recognition.

Buried conductive isolation patterns electrically connect to hinder channel formation, preventing short channel effects while increasing integration density.

Replacing dielectric materials with ferroelectric gate insulators enables denser memory cells while maintaining fast performance speeds.

Resistor network generates three distinct voltages to set different pretilt angles, eliminating multiple equipment setups and boosting manufacturing efficiency.

Segmenting detection with wavelength-selective filters reduces stray light interference while maintaining measurement precision for heart rate and blood oxygen.

Parallel-connected photovoltaic layers operate at uniform voltage, boosting current production while avoiding series connection bottlenecks.

Wider bandgap contact layer eliminates photon absorption loss while maintaining electrical conductivity for focal plane arrays.

A memory cell uses a thermal electrode to heat an electret polarizable member for fast programming.

Stacked oxygen-deficient transition metal oxide layers enable reversible resistance switching via local quality control.

A 3D semiconductor memory device uses a conformal data storage layer on corrugated sidewalls to suppress vertical charge spread.

Printing solvent outside the display region eliminates coffee ring effect, ensuring uniform film thickness and enabling narrow-frame encapsulation.

Continuous tungsten oxide layers bridge electrodes and auxiliary wiring to lower resistance, solving chemical instability from conventional materials.

Global power lines transmit high voltage directly to selected memory blocks, bypassing word line pad resistance and capacitance to eliminate RC delay.

A memory device uses a dual insulating region with higher thermal conductivity adjacent to the switching element for efficient heat dissipation.

A 3D semiconductor detector uses resistive paths to create a constant vertical electric field for signal charge collection.

A transparent conductive oxide layer doped with group 2 metal elements forms a thin, amorphous electrode structure.

Imine-linked conjugated polymers separate semiconducting from metallic nanotubes, then depolymerize via acid or heat to eliminate inter-tube energetic barriers.

Segmented emission stacks combine red, green, and blue light to enhance color purity while preventing color shift caused by aging.