Solid-State Devices TRIZ Cases

A vertical TFT structure around a penetrating opening packs more transistors into the array substrate while preserving pixel aperture for higher display resolution.

Segmented deep isolation and extended active regions cut pixel cross-talk while preserving gate size in dense CMOS image sensors.

Symmetric main and backup pad placement keeps repaired micro-LED sub-pixels aligned, preserving light output consistency and display uniformity.

Overlapping contact holes and a dam improve thin-film uniformity and match reflectance across tiled display module seams.

A curved anisotropic conductive layer improves micro-LED bonding strength and fixation while reducing ESD during display assembly.

Pneumatic pressure and adhesive protrusions improve micro LED transfer accuracy on larger substrates, cutting arrangement errors and transfer time.

A tuned green spectrum balances Rec. 2020 color gamut with M-cone stimulation by controlling peak ratios and spectral distribution.

Pixel separation walls and diffusion regions improve phase difference detection while limiting image information loss in autofocus imaging.

Dam wall units between COB LED elements interrupt total internal reflection under the cover layer, increasing output light and display brightness.

Selective etching forms a stilted backside pad that enlarges bond area, improves BSI bondability, and lowers delamination risk.

Metal boundary trenches and oxide pixel trenches cut lateral photon crosstalk while preserving quantum efficiency in CMOS image sensors.

A resin layer joined to a PCB avoids back-side glass wiring, cuts PCB layers, and reduces breakage in LED display module manufacturing.

Hinged pixels and multiple bias-generating pixels cut bias noise, ease glass-substrate manufacturing, and improve sensor isolation.

A back-side deep trench with a doped liner improves pixel isolation, reducing crosstalk and blooming while preserving photodiode area.

Refractive-index layer stacking reflects unconverted blue light back into the color converter, improving display light output efficiency.

A removable protection layer shields the micro lens during planarization, preventing damage and contamination before fiber attachment.

Vertical stacking of micro LEDs and driving chips cuts package size and light loss while enabling active matrix display pixels.

A shielded dual-signal-line pixel layout enables simultaneous adjacent-row readout, preserving frame rate and reducing cross-talk.

An insulating via layout blocks direct ENIG contact with the base, preventing abnormal metal growth while preserving flatness and bond reliability.

Separating the driver chip and micro LED emitters into stacked layers shrinks package area, cuts light loss, and supports higher pixel density.

Lens arrays with high-absorption layers and deep trench isolation boost low-light photodiode efficiency while limiting cross-talk.

Segmented sub-pads replace separate LED wiring, enabling compact series or parallel layouts with lower heat and better reliability.

Nanorod subpixels and a red color conversion layer improve micro LED color resolution, light efficiency, and manufacturability.

Stacked 2D power wiring across APD pixel regions reduces resistance, stabilizes current supply, and supports efficient photon counting at high luminance.

Shared pixel lines and logarithmic conversion improve low-light event detection by expanding dynamic range without sacrificing imaging resolution.

Sequential wet and dry etching clears metal oxides in TFT channel formation, lowering contact resistance and improving display yield.

A vertically stacked micro-LED with color filters increases luminous area for red and green pixels without enlarging pixel footprint.

A stacked transistor-over-emitter layout with a reflective electrode boosts light extraction and reliability in high-resolution display pixels.

A thicker conductive layer replaces fine metal grids in micro LED arrays to improve high-resolution yield, brightness uniformity, and power use.

Grooves in the planarization layer let the PDL cover anode ends, preventing etch exposure, oxidation, short circuits, and uneven brightness.

A same-side wirebondable electrode layout improves SSL die light extraction, current spreading, and manufacturing alignment tolerance.

Ion-implanted isolation replaces mesa etching in micro-LEDs, improving substrate adhesion, limiting sidewall damage, and confining current flow.

A three-stage epitaxial source/drain process adds a shaping section to improve etch selectivity, fin isolation, and doping control at smaller pitches.

Segmented metal portions placed between adjacent data lines raise pixel density and resolution while preserving display aperture.

Specific TADF dopant lifetimes and host energy levels improve triplet use, boosting OLED efficiency and operating life.

Integrated ESD bridges on display connection lines dissipate static charge while shrinking pad-area overhead and protecting pixel circuitry.

Spherical fillers in the optical layer improve light extraction and reduce RGB color differences, helping large display panels maintain image quality.

Glue residue on supporting structures helps retain and align micro-LEDs during transfer, improving placement yield and shortening cycle time.

A 5T SRAM cell uses mid-level bit-line precharge and a reference bit line to shrink cell area while speeding sense amplifier reads.

Through-hole mesa layout and multilayer insulation improve current spreading and block moisture in UV vertical LEDs.

A transparent sidewall-and-ceiling protection film blocks moisture and impurities in image sensors while preserving optics and reducing dark current.

Reflective metal layers and ordered photonic structures steer micro LED light more directionally for efficient AR and VR displays.

Curved substrate surfaces split incident light for phase detection, improving autofocus accuracy and edge-to-edge image sharpness.

Interconnected top and bottom mesa links free panel space, block light cross-talk, and cut power use in dense micro LED arrays.

Wider bank openings improve inkjet placement of color conversion layers in high-resolution displays while reducing light absorption and boosting luminance.

Ramp-based comparator and counter gating cuts ADC power use and noise during CMOS pixel signal conversion.

Adjacent same-function transistors and separated signal paths reduce image quality variation, color mixture, and parasitic capacitance.

An offset light source and added optical element redirect reflected light into shadowed regions, reducing occlusion in compact scanning mirror illumination.

Anisotropic pad sizing and protective openings improve dense Mini LED and Micro LED substrate bonding while limiting oxidation and abnormal growth.

Controlled anti-reflection and metal pattern slopes prevent etching undercut, cut reflection, and improve display substrate yield.