3D Memory Device Segmented Blocks for Parallel Reading
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Solution Overview
Problem
Conventional three-dimensional memory devices face limitations in reading and writing speeds due to the fixed sequence requirement for reading memory cells and suffer from program and read disturbances in non-selected memory cells, affecting device performance.
Innovation Solution
The design includes a three-dimensional memory device with a stacked structure and pillar structures, each comprising a conductive core gate column and a surrounding channel layer, allowing for direct voltage application to the word line of a selected memory cell, enabling independent reading of memory cells without sequential voltage application across different levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If read voltage is sequentially applied to each word line from bottom to top (or top to bottom), then the current value corresponding to each word line can be measured to determine the write state of memory cells, but the reading speed is reduced due to the fixed sequential reading order
Solution Approach 1:
The patent divides the memory array into multiple independently controllable blocks, where each block contains its own bit lines, word lines, and memory cells. This segmentation allows parallel reading operations across different blocks, enabling arbitrary reading order without sequential constraints while maintaining measurement precision through dedicated read circuits for each block.
Solution Approach 2:
The patent introduces a block dimension beyond the traditional two-dimensional word line/column structure. By organizing memory cells into multiple blocks that can be independently selected and read, the system adds a third dimension of access control, allowing parallel reading operations and arbitrary reading sequences without affecting measurement accuracy.
2Quantity of substance
If conventional three-dimensional memory structure with vertically stacked memory layers and vertical channels is used, then storage capacity is increased, but program disturbance and read disturbance occur in non-selected memory cells affecting device performance
Solution Approach 1:
The patent segments the three-dimensional memory into multiple independent blocks with separate control circuits. This segmentation isolates non-selected memory cells from disturbance effects by allowing precise control of voltage application to only the selected block, maintaining high storage capacity through vertical stacking while eliminating program and read disturbance in other blocks.
Solution Approach 2:
The patent introduces block selection circuits and control logic as intermediaries between the control unit and the memory array. These intermediary components enable precise control of voltage application, ensuring that program and read operations affect only the selected block while protecting non-selected blocks from disturbance, thus maintaining reliability alongside high storage capacity.
3Speed
If voltage is applied to multiple word lines simultaneously for reading, then reading speed is improved by allowing arbitrary reading order, but voltage interference between word lines may occur
Solution Approach 1:
The patent divides the memory array into multiple blocks with physically separated word lines and control circuits. This spatial segmentation allows simultaneous voltage application to multiple blocks without interference, as each block's word lines are electrically isolated. This enables parallel reading operations and arbitrary reading order while preventing voltage interference through physical separation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves reading and writing speeds by allowing arbitrary reading of memory cell states and reduces disturbances in non-selected memory cells, enhancing the overall performance of the memory device.
Implementation Method 1
Each of the pillar structures includes an outermost ferroelectric layer, a conductive core gate column, and a surrounding channel layer disposed between the outermost ferroelectric layer and the conductive core gate column
Data Source
AI summary
A three-dimensional memory device and a manufacturing method thereof are provided. The three-dimensional memory device includes a plurality of bottom control gate lines, a plurality of bottom source lines, a stacked structure on the bottom source lines, a plurality of bit lines disposed on the stacked structure, and a plurality of pillar structures passing through the stacked structure. The stacked structure includes a plurality of stacked layers insulated from one another and respectively located at different levels. Each stacked layer includes a plurality of word lines. Each word line and the corresponding pillar structure, which is connected between the corresponding bit line and the corresponding bottom source line, define a memory cell. Each pillar structure includes an outermost ferroelectric layer, a conductive core gate column, and a surrounding channel layer disposed therebetween. The conductive core gate column is electrically connected to the corresponding bottom control gate line.