Non-Volatile Memory Gate Structure Nitride Layer Design
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Solution Overview
Problem
Conventional non-volatile memory technologies face issues with electron drift, which affects operation speed and charge storage capability, and are incompatible with current logic processes, increasing process complexity.
Innovation Solution
A method for manufacturing a non-volatile memory that forms a nitride layer between the gate conductive layer and the substrate, avoiding electron drift and maintaining compatibility with current logic processes by using a gate dielectric layer and forming an L-shaped nitride layer with specific thicknesses and oxidation processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If silicon nitride charge trap layer is disposed on the sidewall of the gate (sidewall type SONOS), then charge storage capability is improved, but electron drift occurs which influences operation speed
Solution Approach 1:
The patent transitions from sidewall-type charge trap configuration to a bottom-type configuration where the nitride layer is positioned at the interface between the gate conductive layer and substrate. This dimensional change eliminates the electron drift pathway while preserving charge storage functionality through the ONO structure at the gate- substrate interface.
Solution Approach 2:
The patent introduces an ONO structure (oxide-nitride-oxide) as an intermediary layer between the gate conductive layer and substrate. This mediator structure prevents direct electron drift while enabling charge trapping, thus resolving the contradiction between charge storage capability and operation speed.
2Reliability
If ONO structure is used to replace gate oxide layer (planar type SONOS), then charge storage is improved, but process complexity increases and compatibility with current logic processes is lost
Solution Approach 1:
The patent merges the charge storage function with the existing gate structure by forming the ONO structure at the gate- substrate interface rather than replacing the gate oxide layer. This integration approach maintains compatibility with current logic processes while achieving charge storage functionality.
Solution Approach 2:
The gate structure in the patent serves multiple functions: it acts as both the control gate for device operation and as part of the charge storage structure through the integrated ONO layer. This multi-functionality eliminates the need for separate charge storage structures, reducing process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the efficiency of programming/erasing at lower operation voltages without increasing process complexity, maintaining compatibility with existing logic processes and avoiding electron drift issues.
Implementation Method 1
a first oxide layer is formed on a sidewall and bottom of the gate conductive layer, and a second oxide layer is formed on a surface of the substrate
Data Source
AI summary
A method for manufacturing a non-volatile memory is disclosed. A gate structure is formed on a substrate and includes a gate dielectric layer and a gate conductive layer. The gate dielectric layer is partly removed, thereby a symmetrical opening is formed among the gate conductive layer, the substrate and the gate dielectric layer, and a cavity is formed on end sides of the gate dielectric layer. A first oxide layer is formed on a sidewall and bottom of the gate conductive layer, and a second oxide layer is formed on a surface of the substrate. A nitride material layer is formed covering the gate structure, the first and second oxide layer and the substrate and filling the opening. An etching process is performed to partly remove the nitride material layer, thereby forming a nitride layer on a sidewall of the gate conductive layer and extending into the opening.