Vertical TFT Array Substrate Layout for High-PPI Display Panels
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Solution Overview
Problem
The development of high-resolution display devices is restricted by the large area occupied by thin film transistors, which lowers the pixel aperture ratio and resolution of display panels due to limitations in process line width and wiring.
Innovation Solution
The array substrate design includes a first thin film transistor layer with a vertical configuration, where each transistor has a first electrode, a second electrode, a first active pattern, and a first gate electrode, with at least two sidewalls of the electrodes surrounding a penetrating opening, allowing for a dense array arrangement that maximizes the number of transistors per unit area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the area occupied by thin film transistors is increased to accommodate more transistors per unit area, then the number of thin film transistors increases, but the pixel aperture ratio decreases
Solution Approach 1:
The patent transitions from a planar thin film transistor structure to a vertical three-dimensional structure by extending the active pattern, source electrode, and drain electrode in the thickness direction. This dimensional change allows multiple transistors to be packed more densely in the horizontal plane without increasing their footprint area, thereby increasing the number of transistors per unit area while maintaining pixel aperture ratio.
2Manufacturing precision
If the process line width and wiring are reduced to increase resolution, then more transistors can fit per unit area, but the manufacturing complexity increases
Solution Approach 1:
By moving to a vertical transistor structure, the patent reduces the horizontal footprint of each transistor, which relaxes the requirements for process line width and wiring density. The vertical configuration allows for larger feature sizes in the horizontal plane while still achieving high transistor density, thereby reducing manufacturing complexity.
3Area of stationary object
If vertical thin film transistors are arranged in an array with electrodes surrounding a common opening, then space utilization is maximized, but the device structure becomes more complex
Solution Approach 1:
The patent merges multiple transistor components (source electrodes, drain electrodes, active patterns) that surround a common opening, allowing multiple transistors to share the same vertical space. This merging approach maximizes horizontal space utilization by arranging transistors in a compact array configuration where adjacent transistors share common structural elements.
Solution Approach 2:
The common opening structure serves multiple functions: it acts as the active region for multiple transistors simultaneously, provides a shared vertical channel, and enables compact routing of electrodes. This multi-functional design achieves high space utilization while controlling structural complexity through functional integration.
Data Source
AI summary
An array substrate and a manufacturing method thereof, and a display panel are provided. A first thin film transistor includes a first electrode, a second electrode, a first active pattern, and a first gate electrode. The first active pattern extends in a thickness direction of the array substrate. The first gate extends in the thickness direction of the array substrate. At least two of first sidewalls of the first electrode of the first thin film transistor and at least two second sidewalls of the second electrode of the first thin film transistor are disposed surround a first opening which penetrating the first thin film transistor.