Poly-Insulator-Poly Capacitor Integration in NVM
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Solution Overview
Problem
Conventional capacitors in integrated circuits, such as metal-insulator-metal (MIM) and metal-on-metal (MOM) capacitors, are not conducive to high voltage applications and require additional masks, leading to increased manufacturing costs and larger footprints, which is undesirable for split gate non-volatile memory (NVM) ICs.
Innovation Solution
The integration of poly-insulator-poly (PIP) capacitors within semiconductor devices, where a capacitor isolation region is formed on a substrate, and the capacitor includes a control gate stack, sidewall dielectric layers, and capacitor gates, allowing for high voltage applications without the need for additional masks, thereby reducing manufacturing costs and footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional capacitors (MIM, MOM) are embedded into NVM ICs, then capacitor functionality is achieved, but additional masks are required increasing manufacturing complexity and cost
Solution Approach 1:
The patent merges the capacitor formation process with the existing memory cell fabrication process. The capacitor control gate stack is formed using the same control gate electrode layers and dielectric layers that are already being deposited for the memory cells, eliminating the need for separate capacitor-specific masks and process steps.
Solution Approach 2:
The control gate electrode layers and dielectric layers serve dual functions: they form both the memory cell control gates and the capacitor control gates simultaneously. This multi-functional approach allows a single set of process steps to create both functional elements without requiring additional specialized processes.
2Area of stationary object
If conventional capacitors are used in high voltage applications, then capacitor functionality is achieved, but larger footprint is required
Solution Approach 1:
The patent applies different dielectric materials in specific locations within the capacitor structure. The capacitor dielectric layer uses high-k material between the capacitor control gate and capacitor gate, while other regions may use different dielectric materials optimized for their specific functions, allowing high voltage performance in the critical capacitor region without compromising overall device performance.
Solution Approach 2:
The capacitor structure employs composite dielectric stacks including high-k dielectric materials combined with other dielectric layers. This composite approach enables the capacitor to achieve the necessary breakdown voltage for high voltage applications while maintaining a compact footprint through enhanced dielectric properties.
3Ease of manufacture
If conventional capacitors are embedded into NVM ICs, then capacitor functionality is achieved, but manufacturing cost increases
Solution Approach 1:
The capacitor structure utilizes materials and process steps that are already present in the memory cell fabrication sequence. The control gate electrode layers, control gate dielectric layers, and sidewall dielectric layers are all formed as part of the memory cell process, making the capacitor formation a byproduct of the existing process rather than an additional cost center.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables cost-effective integrated circuits with embedded capacitors suitable for high voltage applications, reducing manufacturing costs and minimizing device size, while maintaining performance and endurance.
Implementation Method 1
the first capacitor sidewall dielectric layer serves as the capacitor dielectric between the first and second capacitor plates
Data Source
AI summary
Devices and methods of forming a device are disclosed. A substrate is prepared with a memory region and a capacitor region. Split non-volatile memory (NVM) cell may be formed in the memory region and a capacitor may be formed in a capacitor region. The split NVM cell and the capacitor are formed with the same gate electrode and dielectric layers. The capacitor may be a poly-insulator-poly (PIP) which may include first and second capacitor control gate stacks or capacitor plates. In the case of capacitor control gate stacks, the capacitor is integrated into the device without the need of an additional mask. In the case of capacitor plates, the capacitor is integrated into the device with only one additional mask.