3D Semiconductor Memory Device Sidewall Data Storage Layer
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Solution Overview
Problem
The integration of planar semiconductor memory devices is limited by high manufacturing costs and reliability issues due to the complexity of fine patterning technologies required for high-density memory cells.
Innovation Solution
A three-dimensional (3D) semiconductor memory device is fabricated with a stack structure featuring alternately stacked gate and insulating patterns, a channel structure connected to the substrate, and a data storage layer, which includes a charge storage layer that suppresses vertical charge spread by conformally covering the sidewalls, thereby enhancing reliability and reducing data loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar semiconductor memory devices use fine patterning technology to increase integration density, then memory cell density improves, but manufacturing cost increases and reliability deteriorates
Solution Approach 1:
The patent transitions from planar (2D) memory cell arrangement to three-dimensional (3D) stacking architecture, where memory cells are arranged vertically across multiple layers. This dimensional change allows high integration density without requiring extreme fine patterning, thereby maintaining reliability while achieving high capacity.
Solution Approach 2:
The memory device is divided into multiple stacked layers, each containing memory cells arranged in a simplified pattern. This segmentation distributes the integration complexity across layers rather than requiring ultra-fine patterning in a single plane, reducing manufacturing difficulty and improving reliability.
2Quantity of substance
If planar semiconductor memory devices use fine patterning technology to increase integration density, then memory cell density improves, but manufacturing cost increases
Solution Approach 1:
By stacking memory cells vertically in three dimensions, the patent achieves high integration density without relying on costly extreme ultraviolet (EUV) or other advanced fine patterning processes. The lateral patterning requirements are relaxed, using more cost-effective fabrication techniques.
Solution Approach 2:
The memory structure is segmented into multiple layers that can be fabricated using standard patterning processes. Each layer uses conventional patterning dimensions, avoiding the need for expensive sub-10nm fine patterning equipment and processes.
3Reliability
If data storage layer conformally covers sidewalls to suppress charge spread, then charge retention improves, but manufacturing complexity increases
Solution Approach 1:
The data storage layer is applied conformally only on the sidewalls of the stack structure, providing localized charge suppression exactly where needed at the interface between storage and channel regions. This targeted approach achieves high charge retention without requiring complex modifications throughout the entire device structure.
Solution Approach 2:
The patent uses vertical stacking to create well-defined sidewall surfaces that enable uniform conformal coverage of the data storage layer. The three-dimensional architecture provides natural surfaces for conformal deposition, simplifying the manufacturing of this complex functional layer compared to planar alternatives.
Data Source
AI summary
A three-dimensional (3D) semiconductor memory device includes an electrode separation pattern, a stack structure, a data storage layer, and a channel structure. The electrode separation pattern is disposed on a substrate. A stack structure is disposed on a sidewall of the electrode separation pattern. The stack structure includes a corrugated sidewall opposite to the sidewall of the electrode separation pattern. The sidewall of the electrode separation pattern is vertical to the substrate. A data storage layer is disposed on the corrugated sidewall. A channel structure is disposed on the charge storage layer.