3D NAND Memory Arrays with Silicon-Rich Trenches for Storage Density
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Solution Overview
Problem
Current methods for forming arrays of elevationally-extending strings of memory cells, such as NAND cells, face challenges in efficiently integrating vertically-stacked memory cells with effective charge-blocking and charge-storage materials, while maintaining control over read and write access.
Innovation Solution
The method involves forming a stack with vertically-alternating insulative tiers and wordline tiers, creating horizontally-elongated trenches, and using a silicon-containing material with at least 30 atomic percent of elemental-form silicon or a silicon-containing alloy, along with charge-blocking and charge-storage materials, to enable efficient memory cell formation and access control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertically-stacked memory cells are integrated with charge-blocking and charge-storage materials, then memory storage capability is improved, but manufacturing complexity increases
Solution Approach 1:
The memory structure is divided into distinct vertically-stacked segments including charge-blocking materials, charge-storage materials, and insulative materials arranged in alternating tiers. This segmentation enables independent formation and control of each functional layer, improving storage capability while managing manufacturing complexity through modular construction
Solution Approach 2:
The patent transitions from planar memory cell arrangements to three-dimensional vertically-stacked configurations. By extending memory cells in the vertical dimension with multiple tiers of functional materials, storage density is significantly improved while the layered structure provides clear manufacturing pathways
2Reliability
If control over read and write access is maintained in vertically-stacked memory cells, then memory access reliability is improved, but device complexity increases
Solution Approach 1:
Wordline tiers are segmented and positioned at different vertical levels to selectively control access to specific memory cell tiers. This segmentation enables independent read/write operations on different memory layers, improving access reliability while maintaining manageable device complexity through hierarchical control
Solution Approach 2:
Control lines and wordlines are extended into the vertical dimension to interface with stacked memory cells at different heights. This three-dimensional control architecture enables selective access to specific memory tiers, improving reliability by isolating access control to specific regions while the vertical arrangement actually reduces overall device footprint
3Reliability
If silicon-containing material with at least 30 atomic percent elemental-form silicon is used, then charge management is improved, but manufacturing precision requirements increase
Solution Approach 1:
The silicon-containing material is specified with a compositional parameter of at least 30 atomic percent elemental-form silicon. This parameter change optimizes charge management properties by balancing the crystalline structure benefits of elemental silicon with the processing advantages of silicon alloys, improving reliability while maintaining manufacturability
Solution Approach 2:
Silicon-containing alloys with at least 30 atomic percent elemental-form silicon are used as composite materials that combine the charge management benefits of crystalline silicon with the manufacturing advantages of alloy systems. These composite materials provide improved charge management while being compatible with existing semiconductor fabrication processes
Data Source
AI summary
An array of elevationally-extending strings of memory cells comprises a vertical stack of alternating insulative tiers and wordline tiers. The wordline tiers have terminal ends corresponding to control-gate regions of individual memory cells. The control-gate regions individually comprise part of a wordline in individual of the wordline tiers. A charge-blocking region of the individual memory cells extends elevationally along the individual control-gate regions. Charge-storage material of the individual memory cells extends elevationally along individual of the charge-blocking regions. Channel material extends elevationally along the vertical stack. Insulative charge-passage material is laterally between the channel material and the charge-storage material. Elevationally-extending walls laterally separate immediately-laterally-adjacent of the wordlines. The walls comprise laterally-outer insulative material and silicon-containing material spanning laterally between the laterally-outer insulative material. The silicon-containing material comprises at least 30 atomic percent of at least one of elemental-form silicon or a silicon-containing alloy. Other aspects, including method, are also disclosed.