Single-Layer Gate EEPROM Cell for System-on-Chip Integration
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Solution Overview
Problem
The integration of EEPROM devices with stacked gate structures into System-on-Chip (SOC) products is complicated due to the mismatch in fabrication technologies with logic devices using single gate structures, leading to issues such as read errors from over-erased unit cells and the need for high program and erasure voltages, which hinder the development of high-performance embedded EEPROM devices.
Innovation Solution
A single-layer gate EEPROM device with a cell array structure that includes unit cells sharing a common well region, featuring a floating gate, selection gate, and active regions with specific impurity regions, and a method of operating the device using hot carrier injection for programming and band-to-band tunneling for erasure, allowing for reduced program and erasure voltages and improved integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a stacked gate structure (floating gate + control gate) is used in EEPROM devices, then data storage capability is improved, but fabrication technology compatibility with logic devices deteriorates
Solution Approach 1:
The patent extracts and removes the control gate from the traditional stacked gate structure, retaining only the floating gate. This simplification eliminates the fabrication incompatibility with logic devices while preserving the essential data storage function through hot carrier injection and band-to-band tunneling mechanisms.
Solution Approach 2:
The single-layer gate EEPROM cell is designed to be universally compatible with standard CMOS fabrication processes used for logic devices. By using the same single-poly layer for both EEPROM cells and logic transistors, the structure achieves multi-functionality across different device types within the same chip, enabling SOC integration.
2Ease of manufacture
If a single-layer gate structure is used to simplify fabrication, then fabrication compatibility with logic devices is improved, but data storage reliability deteriorates
Solution Approach 1:
The patent changes the operational parameters by utilizing high electric field effects (hot carrier injection and band-to-band tunneling) to achieve reliable data storage in a single-layer gate structure. This allows the simplified structure to attain the same functional reliability as complex stacked gate structures through different physical mechanisms.
3Reliability
If high program and erasure voltages are applied to ensure data programming and erasure, then data storage capability is improved, but power consumption increases
Solution Approach 1:
The patent employs periodic pulsed voltage applications rather than continuous high voltages. Program and erasure operations use time-limited pulses (e.g., 10-100 microseconds) to induce hot carrier injection and band-to-band tunneling, achieving complete data programming/erasure with minimal energy consumption compared to sustained high voltage applications.
4Speed
If unit cells are arranged in a NOR-type cell array for fast access time, then access speed is improved, but read errors from over-erased unit cells occur
Solution Approach 1:
The patent applies local quality by creating distinct impurity regions (first, second, and third impurity regions) with different doping concentrations and profiles within the active region. This local differentiation enables precise control of carrier generation and collection, preventing over-erasure effects while maintaining fast NOR-type access speeds through optimized electric field distribution in specific areas.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables the fabrication of high-performance embedded EEPROM devices with reduced power consumption, lower program and erasure voltages, and improved reliability by preventing read and program disturbances, while simplifying the integration with logic devices in SOC products.
Implementation Method 1
featuring a floating gate, selection gate, and active regions with specific impurity regions, and a method of operating the device using hot carrier injection for programming
Implementation Method 2
a method of operating the device using hot carrier injection for programming and band-to-band tunneling for erasure
Data Source
AI summary
A cell array portion of a single-layer gate EEPROM device includes a plurality of unit cells formed over a substrate to share a first well region in the substrate. Each of the plurality of unit cells includes a floating gate having a first part disposed over the first well region and a second part extending from the first part to have a stripe shape, a selection gate spaced apart from the floating gate and disposed to be parallel with the second part of the floating gate, and an active region disposed in the substrate to intersect the floating gate and the selection gate.