Non-Volatile Memory Gate Insulation Oxidation
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Solution Overview
Problem
Three-dimensional non-volatile memory devices, such as PBiCS flash memory, face reliability issues due to thin ONO layers causing low breakdown voltage and inadequate space for channel formation, leading to increased threshold voltage and potential memory cell failure.
Innovation Solution
A method involving the formation of a first gate electrode layer with a sacrificial layer, followed by alternating stacks of inter-layer dielectric and sacrificial layers, channel hole formation, oxidation of the gate electrode surface, and deposition of a channel layer and memory layer to enhance gate insulation and secure channel spaces, allowing for higher voltage application without compromising memory hole filling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the ONO layer thickness is increased to improve breakdown voltage and reliability, then the memory holes having narrow width are filled with the ONO layer and the space where channels are to be formed cannot be secured
Solution Approach 1:
The gate insulation layer is segmented into two distinct parts: a first gate insulation layer formed within the memory holes and a second gate insulation layer formed in the space where channels will be formed. This segmentation allows each layer to be optimized independently for its specific function, resolving the contradiction between achieving sufficient insulation thickness for reliability and maintaining adequate space for channel formation.
Solution Approach 2:
Different regions are assigned different insulation layer configurations: the memory holes receive a first gate insulation layer with specific thickness characteristics, while the channel formation space receives a second gate insulation layer. This local differentiation ensures that each region has the appropriate insulation properties for its intended function without compromising the other.
2Volume of moving object
If the ONO layer is deposited thinner in the space from which the sacrificial layer is removed to improve channel space, then breakdown voltage becomes too low to apply high voltage to the pipe gate electrode layer
Solution Approach 1:
The gate insulation structure is divided into spatially separated components: the first gate insulation layer occupies the memory hole region providing necessary insulation for high voltage application, while the second gate insulation layer occupies the channel formation space. This segmentation resolves the contradiction by providing sufficient insulation thickness locally where high voltage is applied, while simultaneously preserving space where channels need to form.
3Reliability
If the ONO layer thickness is increased overall to improve reliability, then the memory holes having narrow width are filled with the ONO layer and thus the space where the channels are to be formed may not be secured
Solution Approach 1:
The gate insulation is segmented into a first layer formed in memory holes and a second layer formed in channel formation spaces. This allows precise control over the thickness and dimensions of each layer independently, ensuring that narrow memory holes receive adequate insulation without over-filling, while channel spaces maintain appropriate dimensions for subsequent channel formation.
Solution Approach 2:
Different insulation layer configurations are applied to different locations: the first gate insulation layer is optimized for the narrow memory hole geometry, while the second gate insulation layer is optimized for the channel formation space. This local quality approach ensures manufacturing precision is maintained in both regions without compromising reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the reliability of non-volatile memory devices by increasing the gate insulation thickness, reducing threshold voltage variation, and ensuring adequate space for channel formation, thereby enhancing the device's ability to handle high voltages and maintain data integrity.
Implementation Method 1
forming an oxide layer by oxidizing a surface of the first gate electrode layer exposed through the first and second channel holes
Data Source
AI summary
A method for fabricating a non-volatile memory device includes forming a stacked structure where a plurality of inter-layer dielectric layers and a plurality of second sacrificial layers are alternately stacked over the first gate electrode layer, forming a first channel hole that exposes the first sacrificial layer by penetrating through the stacked structure, forming a second channel hole by removing the exposed first sacrificial layer, forming an oxide layer by oxidizing a surface of the first gate electrode layer exposed through the first and second channel holes, forming a channel layer in the first and second channel holes, and forming second gate electrode layers in spaces from which the second sacrificial layers are removed, wherein a memory layer is interposed between the channel layer and the second gate electrode layer.