Global Power Lines for 3D Memory RC Delay Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing three-dimensional memory devices face challenges in rapidly pulling up word lines to specific voltages due to increased resistance and capacitance of word line pads, leading to RC delay issues, which hinder memory operations like programming and erasing.
Innovation Solution
The implementation of global power lines that transmit high voltage directly to selected memory blocks, bypassing the RC delay by connecting to gate control lines and transistor units, allowing for rapid voltage pull-up.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the area of word line pads is increased to increase memory capacity, then the memory capacity is improved, but the RC delay of word lines increases
Solution Approach 1:
The invention segments the voltage supply path by introducing global power lines that directly connect to gate control lines in selected memory blocks, separating the high-voltage transmission function from the word line pad structure. This segmentation allows independent optimization of power delivery without increasing word line pad area.
Solution Approach 2:
The invention introduces global power lines as intermediary elements between the power source and memory blocks. These global power lines act as dedicated high-voltage transmission channels that bypass the RC delay issues of word line pads, directly delivering voltage to gate control lines through local driver circuits.
2Quantity of substance
If more layers of word line pads are provided to increase memory capacity, then the memory capacity is improved, but the resistance and capacitance of word line pads increase
Solution Approach 1:
The invention segments the voltage delivery function from the word line pad structure by introducing dedicated global power lines. This allows the word line pads to maintain their original dimensions while providing reliable voltage pull-up through the separate global power line path to selected memory blocks.
Solution Approach 2:
The invention applies preliminary action by pre-charging global power lines to high voltage levels before memory operations. The local driver circuits are prepared to rapidly transfer this pre-charged voltage to gate control lines, ensuring reliable and rapid voltage pull-up without waiting for charge to accumulate through the word line pad RC network.
Data Source
AI summary
A memory device and a control method thereof are provided. The memory device includes I memory blocks, I global power lines and I first local driver modules. Each memory block includes M gate control lines and a plurality of transistor units arranged in M rows. Gates of the transistor units in the m-th row are electrically connected to the m-th gate control line. The I global power lines are electrically connected to I pre-driver circuits and the I memory blocks, respectively. Each first local driver module is electrically connected to one global power line and one memory block. Each first local driver module includes M first local driver circuits. The m-th first local driver circuit is electrically connected to the m-th gate control line.