Transparent Capacitor Structure for Gate Driver in Panel
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Solution Overview
Problem
High-resolution display panels require high-capacitance scan driving circuits, leading to large capacitor structures that increase border width and are not compatible with one-drop filling (ODF) processes due to opaque metal electrodes, resulting in increased costs and process times.
Innovation Solution
A capacitor structure with multiple transparent electrode layers, allowing for reduced border width and compatibility with ODF processes by using a stacked, light-transmittable design that increases capacitance while minimizing area occupation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a general metal capacitor electrode is used, then the capacitor structure can be formed with conventional materials, but it occupies a large area and increases border width
Solution Approach 1:
The patent transitions from a planar capacitor structure to a three-dimensional stacked structure with multiple electrode layers (first transparent capacitor electrode layer, second transparent capacitor electrode layer, and third transparent capacitor electrode layer) arranged in the thickness direction. This vertical stacking increases capacitance by creating multiple capacitor units in series/parallel configuration while reducing the horizontal area occupation, thereby resolving the contradiction between small area and sufficient capacitance performance.
Solution Approach 2:
The patent employs composite material structure combining transparent capacitor electrode layers (such as ITO, IZO, or other transparent conductive materials) with dielectric layers (first dielectric layer and second dielectric layer). This composite structure provides both the necessary electrical properties for capacitance and the transparency required for ODF process compatibility, while the multi-layer composite design optimizes the capacitance-to-area ratio.
2Adaptability or versatility
If an opaque metal electrode is used, then the capacitor can be manufactured with standard processes, but it cannot be applied in one-drop filling (ODF) process
Solution Approach 1:
The patent changes the optical parameter of the capacitor electrode from opaque (metal) to transparent (transparent conductive material such as ITO, IZO, or other transparent materials). This parameter change enables light transmission necessary for the ODF process while maintaining electrical conductivity. The transparent electrode layers allow UV light to pass through for curing photo-curable resins in the ODF process, thereby achieving adaptability to this advanced manufacturing process.
3Reliability
If a large capacitor structure is used for high-resolution display, then sufficient capacitance is achieved, but the border width increases
Solution Approach 1:
The patent utilizes the thickness direction (vertical dimension) to increase capacitance by stacking multiple transparent capacitor electrode layers and dielectric layers. This creates a three-dimensional capacitor structure where capacitance is enhanced through the vertical arrangement of multiple capacitor units, allowing the border width to be reduced while maintaining sufficient capacitance for high-resolution display panels.
4Area of stationary object
If transparent capacitor electrode layers are stacked in thickness direction, then area is reduced and light transmittance is maintained, but structural complexity increases
Solution Approach 1:
The patent segments the capacitor structure into multiple discrete layers: first transparent capacitor electrode layer, first dielectric layer, second transparent capacitor electrode layer, second dielectric layer, and third transparent capacitor electrode layer. Each layer is formed through separate patterning and deposition steps. This segmentation allows for modular manufacturing and facilitates the stacking arrangement that reduces area while maintaining functionality, though it does increase process steps.
Data Source
AI summary
A capacitor structure of gate driver in panel (GIP) includes a first metal layer, a first dielectric layer, a second metal layer, a second dielectric layer, a first and second transparent capacitor electrode layers. The first dielectric layer covers the first metal layer. The second metal layer is disposed on the first dielectric layer and coupled to the first metal layer. The second dielectric layer covers the second metal layer. The first transparent capacitor electrode layer is disposed on the first dielectric layer and connected to the second metal layer. The second transparent capacitor electrode layer is disposed on the second dielectric layer and coupled to the first metal layer, in which the second and first transparent capacitor electrode layers are arranged to be stacked in a thickness direction and mutually opposed across the second dielectric layer therebetween.