Buried Conductive Isolation Patterns for High Density Memory
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Solution Overview
Problem
The high cost of process equipment limits the integration density of semiconductor memory devices, necessitating new technologies to enhance integration without increasing costs.
Innovation Solution
A data storing device with buried conductive isolation patterns and gate line structures, where the conductive isolation patterns are electrically connected and configured to hinder channel region formation, receiving ground or negative voltage, and sharing source regions with gate line structures to prevent short channel effects, allowing for increased integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional isolation structures are used, then device isolation is achieved, but integration density is limited due to process equipment costs and complexity
Solution Approach 1:
The patent merges the isolation structure with the gate line structure by forming both within the same trench using the same gate electrode pattern. This integration eliminates the need for separate isolation trenches and reduces manufacturing steps, directly addressing the contradiction between achieving device isolation and maintaining high integration density while reducing process complexity
Solution Approach 2:
The gate electrode pattern serves multiple functions: it acts as both the gate line for transistor control and as the isolation structure between adjacent devices. This multi-functionality reduces the number of separate structures needed, thereby increasing integration density while simplifying the overall device architecture
2Manufacturing precision
If integration density is increased, then more devices fit on chip, but short channel effects worsen
Solution Approach 1:
The patent transitions from planar gate structures to three-dimensional buried gate structures extending into the substrate. This vertical dimensionality change allows for better electrostatic control of the channel region, suppressing short channel effects while enabling higher integration density through compact device footprints
3Reliability
If separate isolation structures are formed, then device isolation is achieved, but manufacturing steps and costs increase
Solution Approach 1:
The isolation structure and gate line structure are formed as an integrated unit within the same trench, using the same gate electrode pattern and filling process. This merging eliminates separate manufacturing steps for isolation structure formation, reducing both process complexity and manufacturing costs while ensuring reliable device isolation
Data Source
AI summary
A data storing device may include a substrate, transistors on the substrate that include gate line structures, and conductive isolation patterns defining active regions of the transistors. Each conductive isolation pattern includes at least one portion buried in the substrate and the conductive isolation patterns are electrically connected with each other.