Semiconductor Storage Device Layout Uniformity
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Solution Overview
Problem
In semiconductor storage devices with hierarchical bit-line architecture, irregular arrangement of access transistors and bit-line connecting transistors leads to process variations during fabrication, making it difficult to achieve high-density transistor formation and uniform electrical characteristics, which hinders the reduction of layout area and increase in storage capacity.
Innovation Solution
The arrangement of sub memory arrays with aligned sub bit lines and regularly repeated patterns of cell transistors and bit-line connecting transistors along the main bit line, ensuring uniformity and symmetry in the layout pattern.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If access transistors and bit-line connecting transistors are arranged irregularly to connect sub bit lines to main bit lines, then the hierarchical bit-line architecture can be implemented, but process variations during fabrication increase and electrical characteristics cannot be made uniform
Solution Approach 1:
The patent applies asymmetry by intentionally designing irregular arrangements of access transistors and bit-line connecting transistors in specific regions to compensate for process variations. By strategically placing transistors with different characteristics in different locations, the overall electrical characteristics across the chip can be made uniform despite the irregular local arrangements.
Solution Approach 2:
The patent implements local quality by allowing different regions of the chip to have different transistor arrangements and characteristics. Each region is optimized locally to compensate for specific process variations in that area, while maintaining the overall hierarchical bit-line architecture.
2Adaptability or versatility
If access transistors and bit-line connecting transistors are arranged irregularly, then sub bit lines can be connected to main bit lines, but layout area cannot be reduced and storage capacity cannot be increased
Solution Approach 1:
The patent applies segmentation by dividing the memory array into multiple sub-arrays, each with its own access transistors and bit-line connecting transistors. This segmentation allows for more efficient space utilization and reduces the overall layout area while maintaining the hierarchical bit-line architecture.
Solution Approach 2:
The patent utilizes another dimension by arranging transistors and bit lines in a three-dimensional configuration rather than a simple planar layout. This allows for more compact integration and reduced layout area while maintaining electrical performance.
3Adaptability or versatility
If access transistors and bit-line connecting transistors are arranged irregularly, then hierarchical bit-line architecture is maintained, but fabrication yield becomes difficult to enhance
Solution Approach 1:
The patent applies parameter changes by adjusting transistor dimensions, doping concentrations, and other fabrication parameters in different regions to compensate for process variations. This allows for maintaining high fabrication yield despite the irregular transistor arrangements required by the hierarchical bit-line architecture.
Data Source
AI summary
In a semiconductor storage device, either two memory cell gates TG or a memory cell gate TG and a bit-line connecting gate SW are formed in every set of n-type doped regions OD at the intersections with word lines WL or bit-line selecting lines KS. A portion near the center of the set of n-type doped regions OD serves as a source/drain region shared by two gates, whereas portions near both ends thereof serve as source/drain regions for respective gates. Each of the source/drain regions is connected to a storage electrode SN of a memory cell capacitor via a storage contact CA or is connected to a sub bit line or a main bit line via a sub-bit-line contact CH and/or a via of a metal interconnection. A pattern formed of four memory cell gates TG and four bit-line connecting gates SW is repeated.