Wafer Substrate Bonding to Reduce Parasitic Losses
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Solution Overview
Problem
Foundries typically lack the capability to provide wafers with substrates more resistive than low resistivity (LRS), high resistivity (HRS), and silicon-on-insulator (SOI) substrates, limiting device performance improvements due to parasitic substrate losses.
Innovation Solution
A foundry-agnostic post-processing method that involves thinning the silicon handle of wafers to expose a new surface and bonding it to a higher resistivity alternate material substrate, such as glass or fused silica, using oxide bonding processing, thereby enhancing device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If foundries use standard LRS, HRS, or SOI substrates, then manufacturing capability is maintained, but device performance is limited due to parasitic substrate losses
Solution Approach 1:
The substrate system is segmented into two independent parts: the original foundry-submitted wafer (containing device structures) and a separate high-resistivity substrate. This allows each component to be optimized independently - the foundry can use standard manufacturing processes for the wafer, while the high-resistivity substrate is prepared separately and bonded later, resolving the contradiction between manufacturing capability and performance requirements
Solution Approach 2:
The high-resistivity substrate is prepared in advance with appropriate surface treatments and resistivity characteristics before the wafer arrives. This preliminary preparation allows the substrate to be ready for bonding without requiring the foundry to have specialized high-resistivity substrate fabrication capabilities, thus maintaining ease of manufacture while enabling improved device performance
2Reliability
If foundries provide higher resistivity substrates, then parasitic substrate losses are reduced, but foundry processing capacity must be expanded
Solution Approach 1:
The requirement for high-resistivity substrate processing is extracted from the foundry's manufacturing process and transferred to a post-processing stage. The foundry only needs to handle standard substrates, while the high-resistivity substrate preparation and bonding operations are performed separately after wafer fabrication, thus reducing foundry processing complexity while still achieving reduced parasitic losses
Solution Approach 2:
An oxide bonding layer acts as an intermediary between the standard wafer and the high-resistivity substrate. This bonding interface enables the combination of differently processed substrates without requiring the foundry to develop new processing capabilities for high-resistivity materials, thereby maintaining simple foundry operations while achieving improved electrical performance
3Ease of manufacture
If standard substrates are used, then foundry processing is simplified, but noise isolation and quality factor are reduced
Solution Approach 1:
The substrate system is divided into the standard foundry wafer and a separate high-resistivity substrate layer. This segmentation allows the foundry to work with simple, well-established standard substrates while the added high-resistivity layer provides superior noise isolation and quality factor enhancement, resolving the contradiction between manufacturing simplicity and performance requirements
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method improves device performance by reducing parasitic substrate losses, increasing noise isolation, quality factor, and capacitance potential, and is applicable to various wafers from different foundries through optimization of bonding operations.
Implementation Method 1
bonding the new surface to an alternate material substrate that is made of a material that has a greater characteristic resistivity than the material of the silicon handle using oxide bonding processing
Data Source
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AI summary
A foundry-agnostic post-processing method for a wafer is provided. The wafer includes an active surface, a substrate and an intermediate layer interposed between the active surface and the substrate. The method includes removing the wafer from an output yield of a wafer processing foundry, thinning the substrate to the intermediate layer or within microns of the intermediate layer to expose a new surface and bonding the new surface to an alternate material substrate which provides for enhanced device performance as compared to the substrate.