Backside MRAM Layout for Routing and Power Loss Reduction
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Solution Overview
Problem
As device feature size decreases and density increases in semiconductor devices, routing challenges arise in the front-end-of-line (FEOL) layer, particularly with the placement of programmable resistance devices in the back-end-of-line (BEOL) layer, which can obstruct signal and power routing or increase power losses due to resistance and parasitic capacitances.
Innovation Solution
Forming programmable resistance devices on the backside of the FEOL layer, opposite to the BEOL layer, and creating independent backside BEOL layers for power distribution, allowing for additional device placement and reducing resistance and capacitances, while protecting sensitive components from high-temperature fabrication processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If programmable resistance devices are placed in the BEOL layer on the front side, then device density increases, but signal routing is obstructed and power losses increase due to resistance and parasitic capacitances
Solution Approach 1:
The patent moves programmable resistance devices from the traditional front-side BEOL layer to the backside of the FEOL layer, utilizing the unused backside dimension. This dimensional transition allows signal routing to occur on the front side without obstruction from resistance devices, eliminating parasitic capacitance issues while maintaining high device density through efficient space utilization of the backside area.
2Quantity of substance
If device feature size decreases to increase density, then device density increases, but routing challenges arise in the FEOL layer
Solution Approach 1:
By relocating programmable resistance devices to the backside of the FEOL layer, the patent separates signal routing paths from device placement areas. This dimensional separation allows independent optimization of routing complexity in the front-side FEOL layer while maintaining high device density through backside integration, effectively decoupling these two design constraints.
3Adaptability or versatility
If more device layers are added to increase functionality, then device functionality increases, but manufacturing complexity increases due to high-temperature fabrication processes
Solution Approach 1:
The patent segments the device structure into front-side FEOL layer with transistors and backside BEOL layer with programmable resistance devices. This segmentation allows each layer to be optimized for its specific fabrication requirements, with the backside layer using lower-temperature processes suitable for programmable resistance devices, thereby reducing overall manufacturing complexity while maintaining enhanced device functionality.
Data Source
AI summary
Semiconductor devices and methods of forming the same include a front-end-of-line (FEOL) layer that includes a first transistor device. A first back-end-of-line (BEOL) layer is on a front side of the FEOL layer and includes a first electrical connection to the first transistor device. A second BEOL layer is on a back side of the FEOL layer and includes a first BEOL device with a second electrical connection to the first transistor device.