MIEC Memory Device Subtractive Etch Symmetric Contacts

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Solution Overview

Problem

Conventional MIEC-based memory cell access devices formed using additive damascene processes exhibit asymmetric current-voltage characteristics and increased leakage current due to tapered via profiles and surface defects from chemical mechanical planarization, necessitating a more effective fabrication method.

Innovation Solution

The use of a subtractive etch process to form MIEC-based memory cell access devices with symmetrical contact areas between the MIEC material and electrodes, eliminating the need for CMP and thereby reducing surface defects and improving I-V characteristics.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If additive damascene process is used to form MIEC-based access devices, then MIEC material can be deposited within vias, but the via etching process forms a tapered profile leading to asymmetric contact areas between MIEC material and electrodes

Engineering Contradiction:

ImproveMIEC material deposition within viasVSAvoidcontact area symmetry

Core Design Contradiction:

Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent inverts the conventional additive damascene approach by using a subtractive etch process. Instead of filling tapered vias with MIEC material, the method etches through a sacrificial layer to directly form contact holes with vertical profiles, ensuring symmetric contact areas between the MIEC material and both electrodes without requiring CMP planarization.

Inventive Principle:

Principle #13The other way round (Inversion)

2Manufacturing precision

If CMP process is used to remove excess MIEC material, then planarization is achieved, but surface defects are formed on the MIEC material portion

Engineering Contradiction:

Improvesurface planarizationVSAvoidsurface defects

Core Design Contradiction:

Manufacturing precisionVSObject-affected harmful factors

Solution Approach 1:

The patent extracts and eliminates the CMP planarization step from the fabrication process by using a subtractive etch approach. The sacrificial layer is etched away to directly form contact holes, allowing MIEC material to be deposited without subsequent CMP processing, thereby preventing surface defects while maintaining adequate planarization through the etch process itself.

Inventive Principle:

Principle #2Taking out (Extraction)

3Productivity

If tapered via profile is formed during etching, then via formation is achieved, but asymmetric current-voltage characteristics and increased leakage current occur

Engineering Contradiction:

Improvevia formation efficiencyVSAvoiddevice performance

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent inverts the conventional via formation approach by using a subtractive etch process through a sacrificial layer. This method directly creates contact holes with vertical profiles rather than tapered profiles, ensuring symmetric current paths and reducing leakage current while maintaining fabrication efficiency.

Inventive Principle:

Principle #13The other way round (Inversion)

Data Source

PatentUS9773978B1Optimal device structures for back-end-of-line compatible mixed ionic electronic conductors materials

Publication Date: 2017.09.26 INTERNATIONAL BUSINESS MACHINE CORPORATION

AI summary

A mixed ionic electron conductor (MIEC)-based memory cell access device is provided. The MIEC-based memory cell access device includes a MIEC material portion located between a bottom electrode and a top electrode. A contact area between the MIEC material portion and the bottom electrode is substantially the same as a contact area between the MIEC material portion and the top electrode.